Loading lib_com/options.h +1 −1 Original line number Diff line number Diff line Loading @@ -44,7 +44,7 @@ #define MOD_BIT_ALLOC_ROM_TABLE // Just to highlight modification in bit allocation table and to ensure these modifications doesn't affect EVS modes*/ #define SIMPLIFY_CODE_BE // Simplify synthesis loop //#define AFFECT_TEST_VECTOR_BE_dec /* This is related to the CR concerning lead_deindexing */ #define CR_2109_to_2112_cd0_ce0 /* This is related to the CRs include in the 26.444 package of 21-12. Concerns lead_deindexing and */ #if 0 /*These are a list of switches that highlight probable places where IVAS code would need to be added */ Loading lib_dec/lead_deindexing_fx.c +1 −1 Original line number Diff line number Diff line Loading @@ -193,7 +193,7 @@ void re8_decode_base_index_fx( m1 = sub(k1, 1); m2 = 8; move16(); #ifdef AFFECT_TEST_VECTOR_BE_dec #ifdef CR_2109_to_2112_cd0_ce0 l = 1; FOR(i = 0; i < 8; i++) { Loading lib_enc/pre_proc_fx.c +5 −2 Original line number Diff line number Diff line Loading @@ -1068,8 +1068,11 @@ void pre_proc_fx( test(); test(); test(); IF( ( ((st->tcxonly == 0) || !(NE_32(st->core_brate_fx,FRAME_NO_DATA)&&NE_32(st->core_brate_fx,SID_2k40)))&&EQ_16(st->L_frame_fx,L_FRAME16k)&&EQ_16(st->codec_mode,MODE2))|| ( EQ_16(st->L_frame_fx,L_FRAME16k) && EQ_16(st->codec_mode,MODE1) ) ) #ifndef CR_2109_to_2112_cd0_ce0 IF((((st->tcxonly == 0) || !(NE_32(st->core_brate_fx, FRAME_NO_DATA) || NE_32(st->core_brate_fx, SID_2k40))) && EQ_16(st->L_frame_fx, L_FRAME16k) && EQ_16(st->codec_mode, MODE2)) || (EQ_16(st->L_frame_fx, L_FRAME16k) && EQ_16(st->codec_mode, MODE1)) ) #else IF((((st->tcxonly == 0) || !(NE_32(st->core_brate_fx,FRAME_NO_DATA) && NE_32(st->core_brate_fx,SID_2k40))) && EQ_16(st->L_frame_fx,L_FRAME16k) && EQ_16(st->codec_mode,MODE2)) || ( EQ_16(st->L_frame_fx,L_FRAME16k) && EQ_16(st->codec_mode,MODE1))) #endif { /* update signal buffers */ Copy( new_inp_resamp16k, st->buf_speech_enc+L_FRAME16k, L_FRAME16k ); Loading Loading
lib_com/options.h +1 −1 Original line number Diff line number Diff line Loading @@ -44,7 +44,7 @@ #define MOD_BIT_ALLOC_ROM_TABLE // Just to highlight modification in bit allocation table and to ensure these modifications doesn't affect EVS modes*/ #define SIMPLIFY_CODE_BE // Simplify synthesis loop //#define AFFECT_TEST_VECTOR_BE_dec /* This is related to the CR concerning lead_deindexing */ #define CR_2109_to_2112_cd0_ce0 /* This is related to the CRs include in the 26.444 package of 21-12. Concerns lead_deindexing and */ #if 0 /*These are a list of switches that highlight probable places where IVAS code would need to be added */ Loading
lib_dec/lead_deindexing_fx.c +1 −1 Original line number Diff line number Diff line Loading @@ -193,7 +193,7 @@ void re8_decode_base_index_fx( m1 = sub(k1, 1); m2 = 8; move16(); #ifdef AFFECT_TEST_VECTOR_BE_dec #ifdef CR_2109_to_2112_cd0_ce0 l = 1; FOR(i = 0; i < 8; i++) { Loading
lib_enc/pre_proc_fx.c +5 −2 Original line number Diff line number Diff line Loading @@ -1068,8 +1068,11 @@ void pre_proc_fx( test(); test(); test(); IF( ( ((st->tcxonly == 0) || !(NE_32(st->core_brate_fx,FRAME_NO_DATA)&&NE_32(st->core_brate_fx,SID_2k40)))&&EQ_16(st->L_frame_fx,L_FRAME16k)&&EQ_16(st->codec_mode,MODE2))|| ( EQ_16(st->L_frame_fx,L_FRAME16k) && EQ_16(st->codec_mode,MODE1) ) ) #ifndef CR_2109_to_2112_cd0_ce0 IF((((st->tcxonly == 0) || !(NE_32(st->core_brate_fx, FRAME_NO_DATA) || NE_32(st->core_brate_fx, SID_2k40))) && EQ_16(st->L_frame_fx, L_FRAME16k) && EQ_16(st->codec_mode, MODE2)) || (EQ_16(st->L_frame_fx, L_FRAME16k) && EQ_16(st->codec_mode, MODE1)) ) #else IF((((st->tcxonly == 0) || !(NE_32(st->core_brate_fx,FRAME_NO_DATA) && NE_32(st->core_brate_fx,SID_2k40))) && EQ_16(st->L_frame_fx,L_FRAME16k) && EQ_16(st->codec_mode,MODE2)) || ( EQ_16(st->L_frame_fx,L_FRAME16k) && EQ_16(st->codec_mode,MODE1))) #endif { /* update signal buffers */ Copy( new_inp_resamp16k, st->buf_speech_enc+L_FRAME16k, L_FRAME16k ); Loading