Loading lib_dec/ivas_mdct_core_dec.c +4 −22 Original line number Diff line number Diff line Loading @@ -151,41 +151,23 @@ static void dec_prm_tcx_sidebits( if ( ( st->last_core == ACELP_CORE && st->last_total_brate == FRAME_NO_DATA ) || st->prev_bfi ) { /* needed for cases where first TCX frame after a certain transition (e.g. inactive SID/zero frame -> active or stereo switching) is lost */ #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 if ( st->core == TCX_20_CORE ) { st->last_core_from_bs = get_next_indice( st0, 1 ); } else { st->last_core_from_bs = st->last_core; } #else st->last_core_from_bs = get_next_indice( st0, 1 ); #endif /* ACELP -> TCX_10 transitions are forbidden */ #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 /* put under this switch for documentation, even though it is actually a general bug */ if ( st->core == TCX_10_CORE && st->last_core == ACELP_CORE ) #else if ( st->core == TCX_10_CORE && st->last_core == ACELP_CORE && st->last_total_brate == FRAME_NO_DATA ) #endif { st->last_core = TCX_20_CORE; #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 st->last_core_from_bs = st->last_core; #endif } } else { #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 if ( st->core != TCX_10_CORE ) { st->last_core = get_next_indice( st0, 1 ); st->last_core_from_bs = st->last_core; } #else st->last_core = get_next_indice( st0, 1 ); st->last_core_from_bs = st->last_core; #endif } #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 getTCXWindowing( st->core, st->last_core, st->element_mode, st->hTcxCfg, st0 ); Loading lib_dec/ivas_tcx_core_dec.c +0 −11 Original line number Diff line number Diff line Loading @@ -876,18 +876,7 @@ static void dec_prm_tcx( /* last_core for error concealment */ if ( !st->use_partial_copy && st->element_mode != IVAS_CPE_MDCT ) { #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 if ( st->core == TCX_20_CORE ) { st->last_core_from_bs = get_next_indice( st, 1 ); } else { st->last_core_from_bs = st->last_core; } #else st->last_core_from_bs = get_next_indice( st, 1 ); /* Store decoder memory of last_core */ #endif if ( st->last_core == ACELP_CORE && st->last_core_from_bs != ACELP_CORE ) { /* A mismatch between the memory and the last_core Loading lib_enc/ivas_mdct_core_enc.c +0 −7 Original line number Diff line number Diff line Loading @@ -87,14 +87,7 @@ static void enc_prm_pre_mdct( #endif /* write last_core for core switching and error concealment */ #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 if ( st->core == TCX_20_CORE ) { push_next_indice( hBstr, st->last_core != ACELP_CORE, 1 ); } #else push_next_indice( hBstr, st->last_core != ACELP_CORE, 1 ); #endif #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 writeTCXWindowing( hBstr, st->hTcxCfg->tcx_curr_overlap_mode ); Loading lib_enc/ivas_tcx_core_enc.c +0 −14 Original line number Diff line number Diff line Loading @@ -196,11 +196,7 @@ void stereo_tcx_core_enc( st->bits_frame_core = (int16_t) ( st->total_brate / FRAMES_PER_SEC ) - hBstr->nb_bits_tot; /*Get Bits of TCX header*/ #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 nbits_header = 2; /* Coder types (2) */ #else nbits_header = 3; /* Coder types (2) + last_core for bfi (1) */ #endif if ( st->tcxonly ) { Loading Loading @@ -261,9 +257,6 @@ void stereo_tcx_core_enc( { st->core = TCX_20_CORE; n_subframes = 1; #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 nbits_header += 1; /* last core for bfi */ #endif } #ifdef DEBUG_MODE_TCX Loading @@ -284,14 +277,7 @@ void stereo_tcx_core_enc( #endif /* write last_core for error concealment */ #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 if ( st->core == TCX_20_CORE ) { push_next_indice( hBstr, ( st->last_core != ACELP_CORE || st->core == TCX_10_CORE ), 1 ); } #else push_next_indice( hBstr, ( st->last_core != ACELP_CORE || st->core == TCX_10_CORE ), 1 ); #endif /* write TCX overlap mode (1 bit: full, 2 bits: half or no overlap) */ #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 Loading Loading
lib_dec/ivas_mdct_core_dec.c +4 −22 Original line number Diff line number Diff line Loading @@ -151,41 +151,23 @@ static void dec_prm_tcx_sidebits( if ( ( st->last_core == ACELP_CORE && st->last_total_brate == FRAME_NO_DATA ) || st->prev_bfi ) { /* needed for cases where first TCX frame after a certain transition (e.g. inactive SID/zero frame -> active or stereo switching) is lost */ #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 if ( st->core == TCX_20_CORE ) { st->last_core_from_bs = get_next_indice( st0, 1 ); } else { st->last_core_from_bs = st->last_core; } #else st->last_core_from_bs = get_next_indice( st0, 1 ); #endif /* ACELP -> TCX_10 transitions are forbidden */ #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 /* put under this switch for documentation, even though it is actually a general bug */ if ( st->core == TCX_10_CORE && st->last_core == ACELP_CORE ) #else if ( st->core == TCX_10_CORE && st->last_core == ACELP_CORE && st->last_total_brate == FRAME_NO_DATA ) #endif { st->last_core = TCX_20_CORE; #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 st->last_core_from_bs = st->last_core; #endif } } else { #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 if ( st->core != TCX_10_CORE ) { st->last_core = get_next_indice( st0, 1 ); st->last_core_from_bs = st->last_core; } #else st->last_core = get_next_indice( st0, 1 ); st->last_core_from_bs = st->last_core; #endif } #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 getTCXWindowing( st->core, st->last_core, st->element_mode, st->hTcxCfg, st0 ); Loading
lib_dec/ivas_tcx_core_dec.c +0 −11 Original line number Diff line number Diff line Loading @@ -876,18 +876,7 @@ static void dec_prm_tcx( /* last_core for error concealment */ if ( !st->use_partial_copy && st->element_mode != IVAS_CPE_MDCT ) { #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 if ( st->core == TCX_20_CORE ) { st->last_core_from_bs = get_next_indice( st, 1 ); } else { st->last_core_from_bs = st->last_core; } #else st->last_core_from_bs = get_next_indice( st, 1 ); /* Store decoder memory of last_core */ #endif if ( st->last_core == ACELP_CORE && st->last_core_from_bs != ACELP_CORE ) { /* A mismatch between the memory and the last_core Loading
lib_enc/ivas_mdct_core_enc.c +0 −7 Original line number Diff line number Diff line Loading @@ -87,14 +87,7 @@ static void enc_prm_pre_mdct( #endif /* write last_core for core switching and error concealment */ #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 if ( st->core == TCX_20_CORE ) { push_next_indice( hBstr, st->last_core != ACELP_CORE, 1 ); } #else push_next_indice( hBstr, st->last_core != ACELP_CORE, 1 ); #endif #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 writeTCXWindowing( hBstr, st->hTcxCfg->tcx_curr_overlap_mode ); Loading
lib_enc/ivas_tcx_core_enc.c +0 −14 Original line number Diff line number Diff line Loading @@ -196,11 +196,7 @@ void stereo_tcx_core_enc( st->bits_frame_core = (int16_t) ( st->total_brate / FRAMES_PER_SEC ) - hBstr->nb_bits_tot; /*Get Bits of TCX header*/ #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 nbits_header = 2; /* Coder types (2) */ #else nbits_header = 3; /* Coder types (2) + last_core for bfi (1) */ #endif if ( st->tcxonly ) { Loading Loading @@ -261,9 +257,6 @@ void stereo_tcx_core_enc( { st->core = TCX_20_CORE; n_subframes = 1; #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 nbits_header += 1; /* last core for bfi */ #endif } #ifdef DEBUG_MODE_TCX Loading @@ -284,14 +277,7 @@ void stereo_tcx_core_enc( #endif /* write last_core for error concealment */ #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 if ( st->core == TCX_20_CORE ) { push_next_indice( hBstr, ( st->last_core != ACELP_CORE || st->core == TCX_10_CORE ), 1 ); } #else push_next_indice( hBstr, ( st->last_core != ACELP_CORE || st->core == TCX_10_CORE ), 1 ); #endif /* write TCX overlap mode (1 bit: full, 2 bits: half or no overlap) */ #ifdef FIX_IVAS_180_PLC_SIGNAL_LAST_OVLP_IN_TCX10 Loading