Loading lib_com/ivas_rom_com.c +8 −4 Original line number Diff line number Diff line Loading @@ -2786,7 +2786,11 @@ int32_t sep_object_brate[][MAX_NUM_OBJECTS] = {0, 0, 0, 0}, /* 13k2 */ {0, 0, 0, 0}, /* 16k4 */ {9600, 0, 0, 0}, /* 24k4 */ #ifdef OMASA_BRATE_FIX {11000, 0, 0, 0}, /* 32k */ #else {9600, 0, 0, 0}, /* 32k */ #endif {IVAS_13k2, 0, 0, 0}, /* 48k */ #ifdef OMASA_BRATE_FIX {16000, 12500, 0, 0}, /* 64k */ Loading lib_dec/core_switching_dec.c +5 −1 Original line number Diff line number Diff line Loading @@ -1039,7 +1039,11 @@ void bandwidth_switching_detect( { st->bws_cnt1 = 0; } else if ( st->total_brate > ACELP_9k60 && st->last_core_brate < ACELP_9k60 && st->bwidth == SWB && st->last_bwidth == WB ) else if ( st->total_brate > ACELP_9k60 && st->last_core_brate < ACELP_9k60 && st->bwidth == SWB && st->last_bwidth == WB #ifdef OMASA_BRATE // VE: !!!!! TBV // VE: this likely breaks BE in pure ISM !!! && st->last_core_brate != 2450 #endif ) { st->bws_cnt1++; } Loading Loading
lib_com/ivas_rom_com.c +8 −4 Original line number Diff line number Diff line Loading @@ -2786,7 +2786,11 @@ int32_t sep_object_brate[][MAX_NUM_OBJECTS] = {0, 0, 0, 0}, /* 13k2 */ {0, 0, 0, 0}, /* 16k4 */ {9600, 0, 0, 0}, /* 24k4 */ #ifdef OMASA_BRATE_FIX {11000, 0, 0, 0}, /* 32k */ #else {9600, 0, 0, 0}, /* 32k */ #endif {IVAS_13k2, 0, 0, 0}, /* 48k */ #ifdef OMASA_BRATE_FIX {16000, 12500, 0, 0}, /* 64k */ Loading
lib_dec/core_switching_dec.c +5 −1 Original line number Diff line number Diff line Loading @@ -1039,7 +1039,11 @@ void bandwidth_switching_detect( { st->bws_cnt1 = 0; } else if ( st->total_brate > ACELP_9k60 && st->last_core_brate < ACELP_9k60 && st->bwidth == SWB && st->last_bwidth == WB ) else if ( st->total_brate > ACELP_9k60 && st->last_core_brate < ACELP_9k60 && st->bwidth == SWB && st->last_bwidth == WB #ifdef OMASA_BRATE // VE: !!!!! TBV // VE: this likely breaks BE in pure ISM !!! && st->last_core_brate != 2450 #endif ) { st->bws_cnt1++; } Loading