Commit 1c7ee9dc authored by vaclav's avatar vaclav
Browse files

remove debugging stuff; activate IMPR_TC_SWITCHING_MEMORY

parent 5cc0eeaf
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+2 −1
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@

/*#define MEM_COUNT_DETAILS*/                   /* RAM counting tool: print per sub-structure details */

/*#define DEBUG_MODE_INFO*/                     /* output most important parameters to the subdirectory "res/" */
#define DEBUG_MODE_INFO                     /* output most important parameters to the subdirectory "res/" */
#ifdef DEBUG_MODE_INFO
/*#define DEBUG_MODE_ACELP*/                    /* output most important ACELP core parameters to the subdirectory "res/" */
/*#define DEBUG_MODE_TCX*/                      /* output most important TCX core parameters to the subdirectory "res/" */
@@ -150,6 +150,7 @@
#define SBA_INTERN_CONFIG_FIX_HOA2                      /* Issue 99 : Fix for incorrect internal_config when output format is HOA2 or FOA*/
#define FIX_I98_HANDLES_TO_NULL                         /* Issue 98: do the setting of all handles to NULL in one place */
#define SBA_BITRATE_SWITCHING                           /* Issue 114: suppport bitrate switching in SBA */
#define IMPR_TC_SWITCHING_MEMORY                        /* reuse core-coder memory when switching between different number of transport channels */

#define QUANTISE_REAL_FCN_CLEAN_UP                      /*Clean up the ivas_quantise_real_values() function*/

+1 −15
Original line number Diff line number Diff line
@@ -464,7 +464,6 @@ void ivas_dirac_enc_spar_delay_synchro(
    float tmp_buffer[L_FRAME48k];

#ifdef IMPR_TC_SWITCHING_MEMORY
#if 1
    /* check last sba_mode */
    if ( ivas_sba_mode_select( st_ivas->hEncoderConfig->last_ivas_total_brate ) == SBA_MODE_SPAR )
    {
@@ -492,21 +491,8 @@ void ivas_dirac_enc_spar_delay_synchro(
            mvr2r( sts[ch_idx]->input, st_ivas->hDirAC->sba_synchro_buffer[ch_idx], st_ivas->hDirAC->num_samples_synchro_delay );
        }
    }
#else
    /* check last sba_mode */
    if ( ivas_sba_mode_select( st_ivas->hEncoderConfig->last_ivas_total_brate ) == SBA_MODE_SPAR )
    {
        for ( ch_idx = 0; ch_idx < st_ivas->hEncoderConfig->nchan_inp; ch_idx++ )
        {
            mvr2r( data_f[ch_idx], tmp_buffer, input_frame );
            //set_f( data_f[ch_idx], 0, 48 );
            mvr2r( tmp_buffer, &data_f[ch_idx][st_ivas->hDirAC->num_samples_synchro_delay], input_frame - st_ivas->hDirAC->num_samples_synchro_delay );
            mvr2r( &tmp_buffer[input_frame - st_ivas->hDirAC->num_samples_synchro_delay], st_ivas->hDirAC->sba_synchro_buffer[ch_idx], st_ivas->hDirAC->num_samples_synchro_delay );
        }
    }
    else
#endif
#endif

    {
        for ( ch_idx = 0; ch_idx < st_ivas->hEncoderConfig->nchan_inp; ch_idx++ )
        {
+0 −10
Original line number Diff line number Diff line
@@ -235,16 +235,6 @@ ivas_error ivas_enc(
                                  ivas_total_brate, hEncoderConfig->Opt_DTX_ON, st_ivas->nchan_transport == 2 ? st_ivas->hCPE[0]->element_mode : -1 );
            }

            float tmpF = 0;
            dbgwrite( &tmpF, 4, 1, 960, "res/tmp_ppFilterbank_prior_input" );
            if ( st_ivas->nSCE > 0 )
            {
                dbgwrite( st_ivas->hSCE[0]->hCoreCoder[0]->input_buff, 4, 960, 1, "res/tmp_input_buff" );
            }
            else
            {
                dbgwrite( st_ivas->hCPE[0]->hCoreCoder[0]->input_buff, 4, 960, 1, "res/tmp_input_buff" );
            }
        }
        else if ( st_ivas->sba_mode == SBA_MODE_SPAR )
        {
+1 −13
Original line number Diff line number Diff line
@@ -287,8 +287,7 @@ ivas_error ivas_spar_enc(
    hEncoderConfig = st_ivas->hEncoderConfig;

#ifdef IMPR_TC_SWITCHING_MEMORY
    // VE: needs more work - not the right signal segment is used for updating FB memory!!
    // VE2DB: can hFbMixer->ppFilterbank_prior_input be replaced by st->buff ?
    // VE2DB: can hFbMixer->ppFilterbank_prior_input be replaced by st->input ?

    /* check last sba_mode */
    if ( ivas_sba_mode_select( st_ivas->hEncoderConfig->last_ivas_total_brate ) == SBA_MODE_DIRAC )
@@ -319,17 +318,6 @@ ivas_error ivas_spar_enc(

        //VE: TBD - update 'st->input_buff' for SparVAD
    }

    dbgwrite( st_ivas->hSpar->hFbMixer->ppFilterbank_prior_input[0], 4, 960, 1, "res/tmp_ppFilterbank_prior_input" );
    if ( st_ivas->nSCE > 0 )
    {
        dbgwrite( st_ivas->hSCE[0]->hCoreCoder[0]->input_buff, 4, 960, 1, "res/tmp_input_buff" );
    }
    else
    {
        dbgwrite( st_ivas->hCPE[0]->hCoreCoder[0]->input_buff, 4, 960, 1, "res/tmp_input_buff" );
    }

#endif

    /* front VAD */