Loading lib_dec/acelp_core_dec.c +1 −1 Original line number Diff line number Diff line Loading @@ -517,7 +517,7 @@ ivas_error acelp_core_dec( else { #ifdef FIX_ISM_DTX_CNG_BWIDTH_ALT if ( st->core_brate == SID_2k40 && st->element_mode != IVAS_CPE_MDCT && read_sid_info ) if ( st->core_brate == SID_2k40 && st->element_mode != IVAS_CPE_MDCT ) #else if ( st->core_brate == SID_2k40 && st->element_mode != IVAS_CPE_MDCT && st->read_sid_info ) #endif Loading Loading
lib_dec/acelp_core_dec.c +1 −1 Original line number Diff line number Diff line Loading @@ -517,7 +517,7 @@ ivas_error acelp_core_dec( else { #ifdef FIX_ISM_DTX_CNG_BWIDTH_ALT if ( st->core_brate == SID_2k40 && st->element_mode != IVAS_CPE_MDCT && read_sid_info ) if ( st->core_brate == SID_2k40 && st->element_mode != IVAS_CPE_MDCT ) #else if ( st->core_brate == SID_2k40 && st->element_mode != IVAS_CPE_MDCT && st->read_sid_info ) #endif Loading