Commit 66a31adc authored by multrus's avatar multrus
Browse files

[cleanup] accept CR_FIX_586_BPF_DFT_MEM

parent 5633fecf

lib_com/options.h

+0 −1
Original line number Diff line number Diff line
@@ -173,7 +173,6 @@ 
/* any switch which is non-be wrt operation points tested in selection */

/* all switches in this category should start with "CR_" */



#define CR_FIX_586_BPF_DFT_MEM                          /* FhG: issue 586: set input memory of DFT analysis of BPF signal to zero for HQ core to fix issue with PLC and bitrate switching */

#define CR_FIX_ISM_DTX_INFINITE_CNG_ON_TRAILING_SILENCE /* FhG: fix for cng in ISM DTX on sudden silence periods */

#define CR_FIX_698_SBA_MSAN                             /* Dlb: issue 698: Uninitialized memory read in SBA init */

lib_dec/ivas_post_proc.c

+0 −6
Original line number Diff line number Diff line
@@ -226,21 +226,15 @@ void stereo_dft_dec_core_switching( 
            mvr2r( &output[st->L_frame - NS2SA( st->L_frame * FRAMES_PER_SEC, STEREO_DFT32MS_OVL_NS )], hCPE->hStereoDft->buff_LBTCX_mem, NS2SA( st->L_frame * FRAMES_PER_SEC, STEREO_DFT32MS_OVL_NS ) );



            /* BPF */

#ifdef CR_FIX_586_BPF_DFT_MEM

            if ( st->p_bpf_noise_buf && st->core != HQ_CORE )

#else

            if ( st->p_bpf_noise_buf )

#endif

            {

                stereo_dft_dec_analyze( hCPE, st->p_bpf_noise_buf, DFT, 0, st->L_frame, output_frame, DFT_STEREO_DEC_ANA_BPF, 2, 0 );

            }

#ifdef CR_FIX_586_BPF_DFT_MEM

            /* st->p_bpf_noise_buf not updated for HQ core -> skip analysis and set input memory to zero */

            else if ( st->p_bpf_noise_buf && st->core == HQ_CORE )

            {

                set_zero( hCPE->input_mem_BPF[0], STEREO_DFT32MS_OVL_16k );

            }

#endif



            /* TCX */

            stereo_dft_dec_analyze( hCPE, synth, DFT, 0, L_frameTCX, output_frame, DFT_STEREO_DEC_ANA_FB, 0, 0 );