Potential open-loop pitch bug in EVS (4)

In the case of the core switching from ACELP core MODE2 to HQ core MODE1 using MODE1 core switching mechanism, the st->pitch[] values are first computed in the 12.8kHz domain, then altered in core_acelp_tcx20_switching() to 16kHz domain and finally altered once again in acelp_core_switch_enc() to 16*1.25=20kHz domain and quantized for MODE1 core switching. The values at 20kHz domain thus seem to be wrong. The logic seems to be wrong already in the EVS standard and should be corrected.

To debug the issue, one can run e.g. ivas_cod.exe -dtx 16400 32 stv32c bit and look at frame #285 (closed).

Potential fix committed under FIX_I4_OL_PITCH (deactivated so far). It needs a review and verification for the case of DTX when core_acelp_tcx20_switching() is not called in all MODE2 frames, see the condition at line 978 in pre_proc.c:

if ( st->core_brate != FRAME_NO_DATA && st->core_brate != SID_2k40 && st->tcxonly == 0 )
{
    core_acelp_tcx20_switching( ... );
}