From 25bac608fa46dcc3b8c3fea130879a9c28eb1cb5 Mon Sep 17 00:00:00 2001 From: Charles Kinuthia Date: Thu, 30 Mar 2023 11:52:05 +0200 Subject: [PATCH 1/6] ROM optimization for FD-CNG first stage MSVQ - under define ERI_FDCNGVQ_LOW_ROM - inactive define ERI_FDCNGVQ_LOW_ROM_TESTING included for comparing with baseline --- lib_com/cnst.h | 23 +++ lib_com/ivas_error_utils.h | 4 + lib_com/lsf_tools.c | 367 ++++++++++++++++++++++++++++++++++++- lib_com/options.h | 4 + lib_com/prot.h | 54 +++++- lib_com/rom_com.c | 293 +++++++++++++++++++++++++++++ lib_com/rom_com.h | 46 +++++ lib_dec/fd_cng_dec.c | 72 ++++++++ lib_dec/lsf_msvq_ma_dec.c | 13 ++ lib_enc/dtx.c | 4 + lib_enc/fd_cng_enc.c | 283 +++++++++++++++++++++++++++- lib_enc/lib_enc.c | 4 + lib_enc/lsf_msvq_ma_enc.c | 278 +++++++++++++++++++++++++++- 13 files changed, 1437 insertions(+), 8 deletions(-) diff --git a/lib_com/cnst.h b/lib_com/cnst.h index db1dc3d898..b4b41a7d3f 100644 --- a/lib_com/cnst.h +++ b/lib_com/cnst.h @@ -755,7 +755,11 @@ typedef enum #define STEP_SID 5.25f /* CNG & DTX - CNG energy quantization step */ #define MIN_ACT_CNG_UPD 20 /* DTX - Minimum number of consecutive active frames for CNG mode update */ +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING +#define FIXED_SID_RATE 2 /* increase DTX SID rate for better FDCNG VQ testing */ +#else #define FIXED_SID_RATE 8 /* DTX SID rate */ +#endif #define TOTALNOISE_HIST_SIZE 4 @@ -1391,6 +1395,25 @@ enum #define NPARTCLDFB 10 #define NPART_SHAPING 62 +#ifdef ERI_FDCNGVQ_LOW_ROM +#define FDCNG_VQ_MAX_LEN FD_CNG_maxN_37bits +#define FDCNG_VQ_DCT_NSEGM 4 +#define FDCNG_VQ_DCT_MINTRUNC 8 +#define FDCNG_VQ_DCT_MAXTRUNC 18 +#define FDCNG_VQ_MAX_LEN_WB 21 + +#define FDCNG_VQ_DCT_NPOST 8 + +typedef enum _DCTTYPE +{ + DCT_T2_24_XX = 0, /* truncated DCT_T2_24 */ + IDCT_T2_XX_24 = 1, + DCT_T2_21_XX = 2, /* truncated DCT_T2_21 */ + IDCT_T2_XX_21 = 3 +} DCTTYPE; + +#endif + #define MSSUBFRLEN 12 #define MSNUMSUBFR 6 #define MSBUFLEN 5 diff --git a/lib_com/ivas_error_utils.h b/lib_com/ivas_error_utils.h index 034369656b..b49cf309ba 100644 --- a/lib_com/ivas_error_utils.h +++ b/lib_com/ivas_error_utils.h @@ -83,7 +83,11 @@ static inline ivas_error ivas_error_wrapper( const ivas_error error_code, const va_end( args ); fprintf( stderr, "\n\nIn function: %s(), %s:%d\n\n", function, file, line ); +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + assert( 0 ); +#endif // assert( 0 ); + return error_code; } #else diff --git a/lib_com/lsf_tools.c b/lib_com/lsf_tools.c index 19321e21d9..06199959f2 100644 --- a/lib_com/lsf_tools.c +++ b/lib_com/lsf_tools.c @@ -2027,6 +2027,69 @@ int16_t tcxlpc_get_cdk( return cdk; } +#ifdef ERI_FDCNGVQ_LOW_ROM +void dec_FDCNG_MSVQ_stage1( + int16_t j_full, /* i: index full range */ + int16_t n, /* i: dimension to generate */ + const float *invTrfMatrix, /* i: matrix for synthesis */ + const DCTTYPE idcttype, /* i: specify which IDCT */ + float *uq, /* o: synthesized stage1 vector */ + Word16 *uq_ind /* o: synthesized stage1 vector in BASOP */ +) +{ + int16_t col, segm_ind, j; + float dct_vec[FDCNG_VQ_MAX_LEN]; + float idct_vec[FDCNG_VQ_MAX_LEN]; + const Word8 *cbpW8; + const Word16 *dct_col_shift_tab; + + assert( n <= FDCNG_VQ_MAX_LEN ); + assert( n >= FDCNG_VQ_DCT_MINTRUNC ); + + segm_ind = 0; + for ( col = 1; col <= FDCNG_VQ_DCT_NSEGM; col++ ) + { + if ( j_full >= cdk1_ivas_cum_entries_per_segment[col] ) + { + segm_ind++; + } + } + + j = j_full - cdk1_ivas_cum_entries_per_segment[segm_ind]; /* j is the local segment index */ + + assert( j < cdk1_ivas_entries_per_segment[segm_ind] ); + + /* Word8 column variable Qx storage*/ + cbpW8 = cdk_37bits_ivas_stage1_W8Qx_dct_sections[segm_ind]; /* Word8 storage fixed ptr_init */ + cbpW8 += j * cdk1_ivas_cols_per_segment[segm_ind]; /* adaptive ptr init */ + dct_col_shift_tab = stage1_dct_col_syn_shift[segm_ind]; + + for ( col = 0; col < cdk1_ivas_cols_per_segment[segm_ind]; col++ ) + { +#if 1 + dct_vec[col] = (float) ( ( (Word16) cbpW8[col] ) << dct_col_shift_tab[col] ); +#else +#define WMC_TOOL_MAN + dct_vec[col] = (float) ( ( (Word16) cbpW8[col] ) << dct_col_shift_tab[col] ); + LOGIC( 1 ); + SHIFT( 1 ); + ADD( 1 ); /* in BASOP: s_and(for W8->W16), shl(), sub()*/ +#undef WMC_TOOL_MAN +#endif + } + dctT2_N_apply_matrix( (const float *) dct_vec, idct_vec, cdk1_ivas_cols_per_segment[segm_ind], n, invTrfMatrix, FDCNG_VQ_DCT_MAXTRUNC, idcttype ); + + /*scale down to original fdcngvq domain and move to Q0 */ + v_multc( idct_vec, fdcng_dct_scaleF[1], idct_vec, n ); + /* fdcng_dct_scaleF[1] --> 0.0625-->scale down from search Q4 domain to Q0 , not really relevant for BASOP loop */ + + /*add common mid fdcng vector, in fdcng bands domain */ + v_add( idct_vec, cdk1r_tr_midQ_truncQ, uq, n ); + assert( uq_ind == NULL ); +} +#endif + + /*--------------------------------------------------------------------------* * msvq_dec() * @@ -2042,8 +2105,12 @@ void msvq_dec( const int16_t N, /* i : Vector dimension */ const int16_t maxN, /* i : Codebook dimension */ const int16_t Idx[], /* i : Indices */ - float *uq, /* o : quantized vector */ - Word16 *uq_ind /* o : quantized vector (fixed point) */ +#ifdef ERI_FDCNGVQ_LOW_ROM + const int16_t applyIDCT_flag, /* i : applyIDCT flag */ + const float *invTrfMatrix, /* i: matrix for synthesis */ +#endif + float *uq, /* o : quantized vector */ + Word16 *uq_ind /* o : quantized vector (fixed point) */ ) { int16_t i, n, maxn, start; @@ -2079,9 +2146,32 @@ void msvq_dec( start = 0; } +#ifdef ERI_FDCNGVQ_LOW_ROM + if ( i == 0 && applyIDCT_flag != 0 ) + { + assert( start == 0 ); + dec_FDCNG_MSVQ_stage1( Idx[0], N, invTrfMatrix, IDCT_T2_XX_24, uq, uq_ind ); /* IDCT24 used for all synthesis */ + } + else + { + v_add( uq + start, cb[i] + Idx[i] * maxn, uq + start, n ); + } + #define WMC_TOOL_SKIP + IF( uq_ind != NULL ) + { + FOR( j = 0; j < n; ++j ) + { + move16(); + uq_ind[start + j] = add( uq_ind[start + j], (Word16) ( cb[i][Idx[i] * maxn + j] * 2.0f * 1.28f ) ); + } + } +#undef WMC_TOOL_SKIP +#else + v_add( uq + start, cb[i] + Idx[i] * maxn, uq + start, n ); +#define WMC_TOOL_SKIP IF( uq_ind != NULL ) { FOR( j = 0; j < n; ++j ) @@ -2091,6 +2181,7 @@ void msvq_dec( } } #undef WMC_TOOL_SKIP +#endif } return; @@ -2358,3 +2449,275 @@ void a2isf( return; } + +#ifdef ERI_FDCNGVQ_LOW_ROM +/*-------------------------------------------------------------------* + * dctT2_N_apply_matrix() + * + * dct/idct matrix application loop for a fixed DCT basis vector length of N + *-------------------------------------------------------------------*/ +void dctT2_N_apply_matrix( + const float *input, + float *output, + const int16_t dct_dim, + int16_t fdcngvq_dim, + const float *matrix, + const int16_t matrix_row_dim, + DCTTYPE dcttype ) +{ + int16_t i, j, dim_in, dim_out; + int16_t mat_step_col, mat_step_row, mat_step_col_flag; + const float *pt_x, *pt_A; + float tmp_y[FDCNG_VQ_MAX_LEN]; + float *pt_y; + +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + char tmp_str[1024]; + sprintf( tmp_str, "dctT2_%d_apply_mat", fdcngvq_dim ); + push_wmops( tmp_str ); + } +#endif + + /* [optionally] non-square DCT_N and IDCT_N matrix application, + using a stored format of an IDCT_Nx(FDCNG_VQ_DCT_MAXTRUNC) matrix */ + /* effciently parallelized in SIMD */ + + assert( dct_dim <= FDCNG_VQ_DCT_MAXTRUNC ); + assert( fdcngvq_dim <= FDCNG_VQ_MAX_LEN ); + + if ( ( dcttype & 1 ) == 0 ) /* even entries are DCTs */ + { + /* DCT_typeII 24,21 -> XX in worst case */ + dim_in = fdcngvq_dim; + dim_out = dct_dim; + mat_step_col = matrix_row_dim; /* matrix maximum storage size dependent, width of first row in matrix */ + mat_step_row = 0; + mat_step_col_flag = 1; + assert( dcttype == DCT_T2_21_XX || dcttype == DCT_T2_24_XX ); + } + else + { + assert( ( dcttype & 1 ) != 0 ); /* idct */ + dim_in = dct_dim; + dim_out = fdcngvq_dim; + mat_step_col = 1; + mat_step_row = matrix_row_dim; + mat_step_col_flag = 0; + assert( dcttype == IDCT_T2_XX_24 ); + } + + pt_y = tmp_y; + for ( i = 0; i < dim_out; i++ ) + { + pt_x = input; + + *pt_y = 0; + + /* +i(DCT) or +i*maxTrunc(IDCT) */ +#define WMC_TOOL_SKIP + pt_A = &( matrix[i * ( mat_step_row + mat_step_col_flag )] ); /* ptr indexing */ + PTR_INIT( 1 ); +#undef WMC_TOOL_SKIP + for ( j = 0; j < dim_in; j++ ) + { +#define WMC_TOOL_SKIP + *pt_y += ( *pt_x++ ) * ( *pt_A ); + pt_A += mat_step_col; /* step +maxtrunc or 1 */ /* ptr indexing*/ + MAC( 1 ); +#undef WMC_TOOL_SKIP + } + pt_y++; + } + mvr2r( tmp_y, output, dim_out ); +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + pop_wmops(); + } +#endif +} + + +/*-------------------------------------------------------------------* + * extend_dctN_input() + * + * (inputN, dctN) -> idct(N_ext) idct_N matrix application loop for + * extending, extrapolating a DCT basis vector length of N to N_ext + *-------------------------------------------------------------------*/ + +void extend_dctN_input( + const float *input, /* i: input in fdcng domain */ + const float *dct_input, /* i: input in dctN(fdcng) domain */ + const int16_t in_dim, /* i: in_dim==N */ + float *ext_sig, /* o: extended output in fdcng domain */ + const int16_t out_dim, /* i: output total dim */ + float *matrix, /* i: idct synthesis matrix of size N rows , n_cols columns*/ + const int16_t n_cols, /* i: number of columns == truncation length */ + DCTTYPE dcttype ) /* i: matrix operation type */ +{ + int16_t i, j, i_rev; + + const float( *ptr )[FDCNG_VQ_DCT_MAXTRUNC] = (void *) matrix; + +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + char tmp_str[1024]; + sprintf( tmp_str, "extend_dct%d_input", in_dim ); + push_wmops( tmp_str ); + } +#endif + + + /* stored format of an IDCT_Nx(FDCNG_VQ_DCT_MAXTRUNC) matrix */ + assert( in_dim < FDCNG_VQ_MAX_LEN ); + assert( out_dim <= FDCNG_VQ_MAX_LEN ); + assert( out_dim > in_dim ); + assert( n_cols == FDCNG_VQ_DCT_MAXTRUNC ); /* for *ptr[MAX_TRUNC] adressing*/ + + + assert( ( dcttype & 1 ) != 0 ); /* idct tables in use for this basis vector extension */ + + mvr2r( input, ext_sig, in_dim ); /* copy initial part, i.e. only last/tail parts are updated */ + + set_f( &( ext_sig[in_dim] ), 0.0, out_dim - in_dim ); + + i_rev = in_dim; /*ptr init*/ + for ( i = in_dim; i < out_dim; i++ ) + { /* for each extension sample */ + /* i = 21 22 23; + i_rev = 20 19 18; for odd dctII simply reflect basis vector + */ + i_rev--; + + for ( j = 0; j < n_cols; j++ ) /* for each available DCT coeff */ + { + /* DCTcoeff * reflected basis vector */ +#define WMC_TOOL_SKIP + /* these are pure ptr operations */ + ext_sig[i] += dct_input[j] * ptr[i_rev][j]; /* sum up scaled and extended basis vector */ + MAC( 1 ); +#undef WMC_TOOL_SKIP + } + } +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + pop_wmops(); + } +#endif +} + + +/* inititate idct24 FDCNG_VQ_DCT_MAXTRUNCx N matrix in RAM from a Word8+Word16 quantized compressed ROM format */ +void create_IDCT_N_Matrix( float *inv_matrixFloatQ, const int16_t N, const int16_t n_cols, const int16_t alloc_size ) +{ + int16_t c, c1, r, r_flip, W16_val; + int16_t len; /* <=FDCNG_VQ_MAX_LEN */ + int16_t mat_cpy_size; + const Word16 *val_ptr; + const Word8 *idx_ptr; + int8_t idx; +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + char tmp_str[1024]; + sprintf( tmp_str, "create_IDCT_%d_mat", N ); + push_wmops( tmp_str ); + } +#endif + + + val_ptr = unique_idctT2_24coeffsQ16; + idx_ptr = idctT2_24_compressed_idx; + len = FDCNG_VQ_MAX_LEN; + if ( N == FDCNG_VQ_MAX_LEN_WB ) + { + val_ptr = unique_idctT2_21coeffsQ16; + idx_ptr = idctT2_21_compressed_idx; + len = N; + } + + assert( alloc_size >= ( n_cols * len ) ); /* enough space for the full expanded IDCT matrix */ + assert( N <= len ); + W16_val = 0; /* safety init */ + + mat_cpy_size = ( n_cols ) * ( len / 2 ); /* one integer division of "len" */ + + if ( ( len & 1 ) != 0 ) + { /* odd sized DCT with a non-reflected center row */ + mat_cpy_size += n_cols; + } + + for ( c = 0; c < mat_cpy_size; c++ ) + { + idx = idx_ptr[c]; + if ( idx >= 0 ) + { + W16_val = ( val_ptr[idx] ); + } + if ( idx < 0 ) + { + W16_val = -( val_ptr[-idx] ); + } + inv_matrixFloatQ[c] = ( +1.52587890625e-05f ) * ( (float) W16_val ); /* 1.0/2.^16 scaling to a float-"Q0" scaling not done in BASOP */ + } + + { /* a temporary local scope for matrix ptr's */ + /* for even number of coeffs DCT24, + flip symmetry for odd, even used to save 50% further Table ROM */ + /* for odd DCT center is not flipped e.g DCT21 */ + /* float inv_matrixFloatQ[len][FDCNG_VQ_DCT_MAXTRUNC]; */ + + /* use fixed number of columns pointers , to simplify adressing code below */ + float( *ptr )[FDCNG_VQ_DCT_MAXTRUNC] = (void *) inv_matrixFloatQ; + float( *ptr21 )[FDCNG_VQ_MAX_LEN_WB] = (void *) inv_matrixFloatQ; + + if ( n_cols == FDCNG_VQ_DCT_MAXTRUNC ) + { + + assert( ( n_cols & 1 ) == 0 ); + for ( c = 0; c < ( n_cols ); c += 2 ) + { + c1 = c + 1; + r_flip = len - 1; + for ( r = 0; r < ( len / 2 ); r++, r_flip-- ) + { +#define WMC_TOOL_SKIP + /* pure ptr based calculations */ + ptr[r_flip][c] = ptr[r][c]; /* flipped */ + ptr[r_flip][c1] = -ptr[r][c1]; /* flipped and sign swapped */ + + MOVE( 2 ); + MULT( 1 ); /*for negate */ +#undef WMC_TOOL_SKIP + } + } + } + else + { + float sign_swap = 1.0f; + assert( n_cols == FDCNG_VQ_MAX_LEN_WB ); + for ( c = 0; c < ( n_cols ); c++ ) + { + r_flip = len - 1; + sign_swap = 1.0f - 2.0f * ( c & 1 ); /*signsawpp odd columns */ + for ( r = 0; r < ( len / 2 ); r++, r_flip-- ) + { +#define WMC_TOOL_SKIP + /* pure ptr based calculations */ + ptr21[r_flip][c] = sign_swap * ptr21[r][c]; /* flipped and potetially sign swapped */ + + MULT( 1 ); + MOVE( 1 ); +#undef WMC_TOOL_SKIP + } + } + } + } +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + pop_wmops(); + } +#endif +} + + +#endif diff --git a/lib_com/options.h b/lib_com/options.h index 73615a0257..56d5c6b1fc 100755 --- a/lib_com/options.h +++ b/lib_com/options.h @@ -156,6 +156,10 @@ #define OTR_REFERENCE_VECTOR_TRACKING /* FhG: enables the reference position orientation tracking mode */ #endif + +#define ERI_FDCNGVQ_LOW_ROM /* Eri: ~1.6kW Table ROM saving for IVAS FDCNG-VQ */ +/*# define ERI_FDCNGVQ_LOW_ROM_TESTING */ /* Enable testing vs. Baseline for XC SD-measurements , deactivate for WMOPS measurement */ + /* ################## End DEVELOPMENT switches ######################### */ /* clang-format on */ #endif diff --git a/lib_com/prot.h b/lib_com/prot.h index 69cc4e0d32..5f0364536f 100644 --- a/lib_com/prot.h +++ b/lib_com/prot.h @@ -8061,7 +8061,11 @@ void msvq_enc( const float w[], /* i : Weights */ const int16_t N, /* i : Vector dimension */ const int16_t maxN, /* i : Codebook dimension */ - int16_t Idx[] /* o : Indices */ +#ifdef ERI_FDCNGVQ_LOW_ROM + const int16_t applyDCT_flag, /* i : applyDCT flag */ + float *invTrfMatrix, /* i:/o expanded synthesis matrix */ +#endif + int16_t Idx[] /* o : Indices */ ); void msvq_dec( @@ -8072,10 +8076,54 @@ void msvq_dec( const int16_t N, /* i : Vector dimension */ const int16_t maxN, /* i : Codebook dimension */ const int16_t Idx[], /* i : Indices */ - float *uq, /* o : quantized vector */ - Word16 *uq_ind /* o : quantized vector (fixed point) */ +#ifdef ERI_FDCNGVQ_LOW_ROM + const int16_t applyIDCT_flag, /* i : applyIDCT flag */ + const float *invTrfMatrix, /* i: synthesis matrix */ +#endif + float *uq, /* o : quantized vector */ + Word16 *uq_ind /* o : quantized vector (fixed point) */ +); + +#ifdef ERI_FDCNGVQ_LOW_ROM +void dec_FDCNG_MSVQ_stage1( + int16_t j_full, /* i: index full range */ + int16_t n, /* i: dimension to generate */ + const float *invTrfMatrix, /* i: synthesis matrix */ + DCTTYPE idcttype, /* i: idct type */ + float *uq, /* o: synthesized stage1 vector */ + Word16 *uq_ind /* o: synthesized stage1 vector in BASOP */ +); + + +void create_IDCT_N_Matrix( + float *inv_matrixFloatQ, /*i/o: RAM buffer */ + const int16_t N, /* i: DCT length , number of time samples */ + const int16_t n_cols, /*i: number of dct coeffs (as DCt may be truncated */ + + const int16_t alloc_size /*i: RAM buffer size in elements*/ ); + +void dctT2_N_apply_matrix( + const float *input, + float *output, + const int16_t dct_dim, + int16_t fdcngvq_dim, + const float *idctT2_N_16matrixQ16, + const int16_t matrix_1st_dim, + DCTTYPE dcttype ); + +void extend_dctN_input( + const float *input, /* i: input in fdcng domain */ + const float *dct_input, /* i: input in dctN(fdcng) domain */ + const int16_t in_dim, /* i: in_dim==N */ + float *ext_sig, /* o: extended output in fdcng domain */ + const int16_t out_dim, /* i: output total dim */ + float *matrix, /* i: idct matrix of size N rows , n_cols columns*/ + const int16_t n_cols, /* i: number of columns == truncation length */ + DCTTYPE dcttype ); /* i: matrix operation type */ +#endif + void PulseResynchronization( const float *src_exc, /* i : Input excitation buffer */ float *dst_exc, /* o : output excitation buffer */ diff --git a/lib_com/rom_com.c b/lib_com/rom_com.c index b0c0c61978..075881cc4d 100644 --- a/lib_com/rom_com.c +++ b/lib_com/rom_com.c @@ -6036,6 +6036,289 @@ const FD_CNG_SETUP FdCngSetup_swb2 = { 640, 320, sizeof(sidPartitions_swb2)/size const int16_t levels_37bits[FD_CNG_stages_37bits] = { 128, 64, 64, 64, 64, 64 }; const int16_t bits_37bits[FD_CNG_stages_37bits] = { 7, 6, 6, 6, 6, 6 }; +#ifdef ERI_FDCNGVQ_LOW_ROM +/* IDCT_MATRIX_ROM: */ + +const Word16 cdk1_ivas_entries_per_segment[FDCNG_VQ_DCT_NSEGM] = { 16, 17, 17, 78 }; +const Word16 cdk1_ivas_cum_entries_per_segment[FDCNG_VQ_DCT_NSEGM + 1] = { 0, 16 ,33, 50, 128 }; +const Word16 /* DCT trunc_len */ cdk1_ivas_cols_per_segment[FDCNG_VQ_DCT_NSEGM] = { FDCNG_VQ_DCT_MINTRUNC, 10, 16, FDCNG_VQ_DCT_MAXTRUNC }; /* 8, 10, 16, 18 */ +const Word16 /* segment inner DCT trunc_len */ cdk1_ivas_trunc_dct_cols_per_segment[FDCNG_VQ_DCT_NSEGM] = { FDCNG_VQ_DCT_MAXTRUNC - FDCNG_VQ_DCT_MINTRUNC, FDCNG_VQ_DCT_MAXTRUNC - 10 , FDCNG_VQ_DCT_MAXTRUNC - 16 , 0 }; + +/* to get back to FDCNG VQ domain for segment S use : idct as follows */ +/* cdk1r_vec[col, row] = cdk1r_tr_midQ_truncQ(col 1:24 ) + invScaleFQ * idctMat( cdk1_ivas_dct_sS_W8[1:col]<element_mode == EVS_MONO ) ? cdk_37bits : cdk_37bits_ivas; +#endif const float gain_q_offset = ( st->element_mode == EVS_MONO ) ? GAIN_Q_OFFSET_EVS : GAIN_Q_OFFSET_IVAS; +#ifdef ERI_FDCNGVQ_LOW_ROM + invTrfMatrix = (float *) tmpRAM; +#endif + hFdCngCom = ( st->hFdCngDec )->hFdCngCom; sidNoiseEst = hFdCngCom->sidNoiseEst; @@ -987,7 +997,21 @@ void FdCng_decodeSID( index = get_next_indice( st, 7 ); /* MSVQ decoder */ + +#ifdef ERI_FDCNGVQ_LOW_ROM + if ( st->element_mode != EVS_MONO ) + { + create_IDCT_N_Matrix( invTrfMatrix, FDCNG_VQ_MAX_LEN, FDCNG_VQ_DCT_MAXTRUNC, sizeof( tmpRAM ) / ( sizeof( float ) ) ); + msvq_dec( cdk_37bits_ivas, NULL, NULL, FD_CNG_stages_37bits, N, FD_CNG_maxN_37bits, indices, 1, invTrfMatrix, v, NULL ); + } + else + { /* Legacy EVS_MONO MSVQ tables */ + msvq_dec( cdk_37bits, NULL, NULL, FD_CNG_stages_37bits, N, FD_CNG_maxN_37bits, indices, 0, NULL, v, NULL ); + } + +#else msvq_dec( codebooks, NULL, NULL, FD_CNG_stages_37bits, N, FD_CNG_maxN_37bits, indices, v, NULL ); +#endif /* Decode gain */ gain = ( (float) index - gain_q_offset ) / 1.5f; @@ -1993,6 +2017,21 @@ void FdCngDecodeMDCTStereoSID( int16_t indices[FD_CNG_stages_37bits]; int16_t N, i, ch, p, stages; int16_t is_out_ms; +#ifdef ERI_FDCNGVQ_LOW_ROM + float *invTrfMatrix; + float tmpRAM[FDCNG_VQ_MAX_LEN][FDCNG_VQ_DCT_MAXTRUNC]; +#endif + +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + push_wmops( "DecodeMDCTStereoSID" ); + } +#endif + +#ifdef ERI_FDCNGVQ_LOW_ROM + invTrfMatrix = (float *) tmpRAM; + create_IDCT_N_Matrix( invTrfMatrix, FDCNG_VQ_MAX_LEN, FDCNG_VQ_DCT_MAXTRUNC, sizeof( tmpRAM ) / ( sizeof( float ) ) ); +#endif is_out_ms = 0; if ( hCPE->hCoreCoder[0]->cng_sba_flag ) @@ -2036,7 +2075,11 @@ void FdCngDecodeMDCTStereoSID( } /* MSVQ decoder */ +#ifdef ERI_FDCNGVQ_LOW_ROM + msvq_dec( cdk_37bits_ivas, NULL, NULL, stages, N, FD_CNG_maxN_37bits, indices, 1, invTrfMatrix, ms_ptr[ch], NULL ); +#else msvq_dec( cdk_37bits_ivas, NULL, NULL, stages, N, FD_CNG_maxN_37bits, indices, ms_ptr[ch], NULL ); +#endif } dtx_read_padding_bits( sts[1], ( IVAS_SID_5k2 - 4400 ) / FRAMES_PER_SEC ); @@ -2073,6 +2116,11 @@ void FdCngDecodeMDCTStereoSID( } } +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + pop_wmops(); + } +#endif return; } @@ -2095,6 +2143,21 @@ void FdCngDecodeDiracMDCTStereoSID( float gain[CPE_CHANNELS]; int16_t indices[FD_CNG_stages_37bits]; int16_t N, i, ch, p; +#ifdef ERI_FDCNGVQ_LOW_ROM + float *invTrfMatrix; + float tmpRAM[FDCNG_VQ_MAX_LEN][FDCNG_VQ_DCT_MAXTRUNC]; +#endif + +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + push_wmops( "DecDiracMDCTStereoSID" ); + } +#endif + +#ifdef ERI_FDCNGVQ_LOW_ROM + invTrfMatrix = (float *) tmpRAM; /* dynamically filled */ + create_IDCT_N_Matrix( invTrfMatrix, FDCNG_VQ_MAX_LEN, FDCNG_VQ_DCT_MAXTRUNC, sizeof( tmpRAM ) / ( sizeof( float ) ) ); +#endif for ( ch = 0; ch < CPE_CHANNELS; ch++ ) { @@ -2117,7 +2180,11 @@ void FdCngDecodeDiracMDCTStereoSID( gain[1] = gain[0]; /* MSVQ decoder */ +#ifdef ERI_FDCNGVQ_LOW_ROM + msvq_dec( cdk_37bits_ivas, NULL, NULL, FD_CNG_stages_37bits, N, FD_CNG_maxN_37bits, indices, 1, invTrfMatrix, ms_ptr[0], NULL ); +#else msvq_dec( cdk_37bits_ivas, NULL, NULL, FD_CNG_stages_37bits, N, FD_CNG_maxN_37bits, indices, ms_ptr[0], NULL ); +#endif mvr2r( ms_ptr[0], ms_ptr[1], N ); /*inverseMS( N, ms_ptr[0], ms_ptr[1], 1.f );*/ @@ -2156,5 +2223,10 @@ void FdCngDecodeDiracMDCTStereoSID( } } +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + pop_wmops(); + } +#endif return; } diff --git a/lib_dec/lsf_msvq_ma_dec.c b/lib_dec/lsf_msvq_ma_dec.c index 2fa1f3573b..ede93bb162 100644 --- a/lib_dec/lsf_msvq_ma_dec.c +++ b/lib_dec/lsf_msvq_ma_dec.c @@ -187,7 +187,11 @@ int16_t D_lsf_tcxlpc( NumIndices = 1; +#ifdef ERI_FDCNGVQ_LOW_ROM + msvq_dec( lsf_codebook[narrowband][cdk], lsf_dims, lsf_offs, TCXLPC_NUMSTAGES, M, M, indices + NumIndices, 0, NULL, lsf_q, lsf_q_ind ); +#else msvq_dec( lsf_codebook[narrowband][cdk], lsf_dims, lsf_offs, TCXLPC_NUMSTAGES, M, M, indices + NumIndices, lsf_q, lsf_q_ind ); +#endif NumIndices += TCXLPC_NUMSTAGES; @@ -195,7 +199,12 @@ int16_t D_lsf_tcxlpc( { /* Only add contribution if flag is enabled */ + +#ifdef ERI_FDCNGVQ_LOW_ROM + msvq_dec( lsf_ind_codebook[narrowband][cdk], lsf_ind_dims, lsf_ind_offs, TCXLPC_IND_NUMSTAGES, M, M, indices + NumIndices, 0, NULL, lsf_rem_q, lsf_rem_q_ind ); +#else msvq_dec( lsf_ind_codebook[narrowband][cdk], lsf_ind_dims, lsf_ind_offs, TCXLPC_IND_NUMSTAGES, M, M, indices + NumIndices, lsf_rem_q, lsf_rem_q_ind ); +#endif NumIndices += TCXLPC_IND_NUMSTAGES; /* Add to MA-removed vector */ @@ -264,7 +273,11 @@ int16_t dec_lsf_tcxlpc( } /* Decode independent lsf */ +#ifdef ERI_FDCNGVQ_LOW_ROM + msvq_dec( lsf_codebook[narrowband][cdk], lsf_dims, lsf_offs, TCXLPC_NUMSTAGES, M, M, flag + 1, 0, NULL, lsf_q_ignored, lsf_q_ind ); +#else msvq_dec( lsf_codebook[narrowband][cdk], lsf_dims, lsf_offs, TCXLPC_NUMSTAGES, M, M, flag + 1, lsf_q_ignored, lsf_q_ind ); +#endif /* Update flag */ *flag = lsf_ind_is_active( lsf_q_ind, lsf_means[narrowband], narrowband, cdk ); diff --git a/lib_enc/dtx.c b/lib_enc/dtx.c index c99a8faf28..40caf46d58 100644 --- a/lib_enc/dtx.c +++ b/lib_enc/dtx.c @@ -281,7 +281,11 @@ void dtx( } else { +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + hDtxEnc->max_SID = FIXED_SID_RATE; +#else hDtxEnc->max_SID = 3; +#endif } if ( hDtxEnc->max_SID > hDtxEnc->interval_SID ) diff --git a/lib_enc/fd_cng_enc.c b/lib_enc/fd_cng_enc.c index e43b65d56a..0c83e05f8a 100644 --- a/lib_enc/fd_cng_enc.c +++ b/lib_enc/fd_cng_enc.c @@ -39,6 +39,10 @@ #include "options.h" #ifdef DEBUGGING #include "debug.h" +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING +#include +#include +#endif #endif #include #include "rom_enc.h" @@ -513,12 +517,29 @@ void FdCng_encodeSID( float w[32]; float preemph_fac = st->preemph_fac; +#ifdef ERI_FDCNGVQ_LOW_ROM + float *invTrfMatrix; + float tmpRAM[FDCNG_VQ_MAX_LEN][FDCNG_VQ_DCT_MAXTRUNC]; + float dct_target[FDCNG_VQ_DCT_MAXTRUNC]; + float tot_sig_ext[FDCNG_VQ_MAX_LEN]; +#else const float *const *codebooks = ( st->element_mode == EVS_MONO ) ? cdk_37bits : cdk_37bits_ivas; +#endif const float gain_q_offset = ( st->element_mode == EVS_MONO ) ? GAIN_Q_OFFSET_EVS : GAIN_Q_OFFSET_IVAS; +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + push_wmops( "FdCng_encodeSID" ); + } +#endif /* Init */ N = hFdCngEnc->npartDec; +#ifdef ERI_FDCNGVQ_LOW_ROM + invTrfMatrix = (float *) tmpRAM; /* dynamically filled */ + set_zero( v, FDCNG_VQ_MAX_LEN ); +#endif + /* Convert to LOG */ e = 0.f; for ( i = 0; i < N; i++ ) @@ -544,10 +565,37 @@ void FdCng_encodeSID( /* MSVQ encoder */ set_f( w, 1.0f, N ); +#ifdef ERI_FDCNGVQ_LOW_ROM + if ( st->element_mode != EVS_MONO ) + { + /* DCT domain compressed/truncated indices used for first stage */ + /* quantization with stage 1 in DCT24 domain, stages 2 through 6 directly in FDCNG band domain */ + if ( N == FDCNG_VQ_MAX_LEN_WB ) + { + create_IDCT_N_Matrix( invTrfMatrix, N, FDCNG_VQ_DCT_MAXTRUNC, sizeof( tmpRAM ) / ( sizeof( float ) ) ); + /* truncated DCT 21 analysis */ + dctT2_N_apply_matrix( (const float *) v, dct_target, FDCNG_VQ_DCT_MAXTRUNC, N, invTrfMatrix, FDCNG_VQ_DCT_MAXTRUNC, DCT_T2_21_XX ); + /* truncated IDCT21 extension to 24 synthesis */ + extend_dctN_input( v, dct_target, N, tot_sig_ext, FDCNG_VQ_MAX_LEN, invTrfMatrix, FDCNG_VQ_DCT_MAXTRUNC, IDCT_T2_XX_21 ); /* use 18 basis vectors*/ + + mvr2r( tot_sig_ext, v, FDCNG_VQ_MAX_LEN ); /* write extended result as input to VQ stage #1 */ + } + create_IDCT_N_Matrix( invTrfMatrix, FDCNG_VQ_MAX_LEN, FDCNG_VQ_DCT_MAXTRUNC, sizeof( tmpRAM ) / ( sizeof( float ) ) ); + msvq_enc( cdk_37bits_ivas, NULL, NULL, v, levels_37bits, FD_CNG_maxC_37bits, FD_CNG_stages_37bits, w, N, FD_CNG_maxN_37bits, 1, invTrfMatrix, indices ); + msvq_dec( cdk_37bits_ivas, NULL, NULL, FD_CNG_stages_37bits, N, FD_CNG_maxN_37bits, indices, 1, invTrfMatrix, v, NULL ); + } + else + { /* EVS_MONO tables */ + msvq_enc( cdk_37bits, NULL, NULL, v, levels_37bits, FD_CNG_maxC_37bits, FD_CNG_stages_37bits, w, N, FD_CNG_maxN_37bits, 1, NULL, indices ); + msvq_dec( cdk_37bits, NULL, NULL, FD_CNG_stages_37bits, N, FD_CNG_maxN_37bits, indices, 1, NULL, v, NULL ); + } +#else msvq_enc( codebooks, NULL, NULL, v, levels_37bits, FD_CNG_maxC_37bits, FD_CNG_stages_37bits, w, N, FD_CNG_maxN_37bits, indices ); /* MSVQ decoder */ msvq_dec( codebooks, NULL, NULL, FD_CNG_stages_37bits, N, FD_CNG_maxN_37bits, indices, v, NULL ); +#endif + /* Compute gain */ gain = 0.f; @@ -630,6 +678,11 @@ void FdCng_encodeSID( lpc_from_spectrum( hFdCngCom, hFdCngEnc->startBandDec, hFdCngEnc->stopFFTbinDec, preemph_fac ); +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + pop_wmops(); + } +#endif return; } @@ -973,6 +1026,24 @@ void FdCngEncodeMDCTStereoSID( int16_t no_side_flag; int16_t is_inp_ms; +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + float vq_inp[CPE_CHANNELS][NPART]; + float vq_outp[4][CPE_CHANNELS][NPART]; /* XC test several VQ results */ + int16_t indices_test[CPE_CHANNELS][FD_CNG_stages_37bits]; +#endif +#ifdef ERI_FDCNGVQ_LOW_ROM + float tot_sig_ext[FDCNG_VQ_MAX_LEN], dct_target[CPE_CHANNELS][FDCNG_VQ_DCT_MAXTRUNC]; /* 24 +2*18*/ + float *invTrfMatrix; + float tmpRAM[FDCNG_VQ_MAX_LEN][FDCNG_VQ_DCT_MAXTRUNC]; /*24*18*/ + invTrfMatrix = (float *) tmpRAM; /* dynamically filled */ +#endif + +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + push_wmops( "EncMDCTStereoSID" ); + } +#endif + is_inp_ms = 0; if ( hCPE->hCoreCoder[0]->cng_sba_flag == 1 ) { @@ -1023,7 +1094,11 @@ void FdCngEncodeMDCTStereoSID( /* Quantize noise shapes */ for ( ch = 0; ch < CPE_CHANNELS; ch++ ) { +#ifdef ERI_FDCNGVQ_LOW_ROM + /* Normalize MSVQ input */ +#else /* Normalize MSVW input */ +#endif gain[ch] = 0.f; for ( p = N_GAIN_MIN; p < N_GAIN_MAX; p++ ) { @@ -1034,8 +1109,47 @@ void FdCngEncodeMDCTStereoSID( for ( p = 0; p < N; p++ ) { ms_ptr[ch][p] -= gain[ch]; +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + vq_inp[ch][p] = ms_ptr[ch][p]; +#endif + } + +#ifdef ERI_FDCNGVQ_LOW_ROM + } + /* always split channel targetloop */ + + /* extend fdcng envelope from length 21 to a 24 length fdncg domain envelope signal */ + /* High quality cosine smooth basis extension used to not introduce noise in stage#1 DCT24 analysis and subsequent VQ-steps */ + if ( N == FDCNG_VQ_MAX_LEN_WB ) + { + create_IDCT_N_Matrix( invTrfMatrix, N, FDCNG_VQ_DCT_MAXTRUNC, sizeof( tmpRAM ) / ( sizeof( float ) ) ); /*WB: create truncated IDCT21 matrix */ + + for ( ch = 0; ch < CPE_CHANNELS; ch++ ) + { + /* run DCT_N N==21 , truncated at 18/21 ~= 86% , i.e use a bit better better quality in extrapolation , than subsequent DCT24 analysis which is truncated at 75%*/ + + /* truncated DCT 21 analysis */ + dctT2_N_apply_matrix( (const float *) ms_ptr[ch], dct_target[ch], FDCNG_VQ_DCT_MAXTRUNC, N, invTrfMatrix, FDCNG_VQ_DCT_MAXTRUNC, DCT_T2_21_XX ); + + /* extrapolate extend fdcng envelope signal in the fdncg ienvelope/"time" domain using DCT21 basis vectors, + estimated DCT21 coeffs scaling extended basis vectors are used to create extrapolated length 24 input target envelope signal */ + /* this DCT21 extension does not introduce DCT24 coefficient noise for the subsequent dct24 target analysis, and later in IDCT24 synthesis */ + + /* truncated IDCT 21 extension synthesis */ + extend_dctN_input( ms_ptr[ch], dct_target[ch], N, tot_sig_ext, FDCNG_VQ_MAX_LEN, invTrfMatrix /* DCT_N basis vectors */, FDCNG_VQ_DCT_MAXTRUNC, IDCT_T2_XX_21 ); /* use 18 basis vectors*/ + + mvr2r( tot_sig_ext, ms_ptr[ch], FDCNG_VQ_MAX_LEN ); /* write extended result as input to VQ */ +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + mvr2r( ms_ptr[ch], vq_inp[ch], FDCNG_VQ_MAX_LEN ); +#endif } + } + create_IDCT_N_Matrix( invTrfMatrix, FDCNG_VQ_MAX_LEN, FDCNG_VQ_DCT_MAXTRUNC, sizeof( tmpRAM ) / ( sizeof( float ) ) ); /*always create/set up IDCT24 matrix in RAM */ + /* end split */ + for ( ch = 0; ch < CPE_CHANNELS; ch++ ) + { +#endif /* MSVQ */ if ( ch ) { @@ -1046,8 +1160,107 @@ void FdCngEncodeMDCTStereoSID( stages = FD_CNG_stages_37bits; } +#ifdef ERI_FDCNGVQ_LOW_ROM + /* DCT24 domain compressed/truncated indices used for first stage */ + /* mid channel quantization using stages 1 through 6 */ + /* & side channel quantization using stages 1 through 4 */ + + { +#define FDCNG_STAGE1VQ_USE_DCT 1 + +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + char vq_name[1024]; + sprintf( vq_name, "msvq_encF_NEW_CH%d_%d", ch, stages ); + push_wmops( vq_name ); + } +#endif + + + msvq_enc( cdk_37bits_ivas, NULL, NULL, ms_ptr[ch], levels_37bits, FD_CNG_maxC_37bits, stages, weights, N, FD_CNG_maxN_37bits, FDCNG_STAGE1VQ_USE_DCT, invTrfMatrix, indices[ch] ); +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + pop_wmops(); + char vq_name[1024]; + sprintf( vq_name, "msvq_decF_NEW_CH%d_%d", ch, stages ); + push_wmops( vq_name ); + } +#endif + msvq_dec( cdk_37bits_ivas, NULL, NULL, stages, N, FD_CNG_maxN_37bits, indices[ch], FDCNG_STAGE1VQ_USE_DCT, invTrfMatrix, ms_ptr[ch], NULL ); +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + pop_wmops(); + } +#endif + } +#else +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + char vq_name[1024]; + sprintf( vq_name, "msvq_encF_BSL_CH%d_%d", ch, stages ); + push_wmops( vq_name ); + } +#endif msvq_enc( cdk_37bits_ivas, NULL, NULL, ms_ptr[ch], levels_37bits, FD_CNG_maxC_37bits, stages, weights, N, FD_CNG_maxN_37bits, indices[ch] ); +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + pop_wmops(); + char vq_name[1024]; + sprintf( vq_name, "msvq_decF_BSL_CH%d_%d", ch, stages ); + push_wmops( vq_name ); + } +#endif + msvq_dec( cdk_37bits_ivas, NULL, NULL, stages, N, FD_CNG_maxN_37bits, indices[ch], ms_ptr[ch], NULL ); +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + pop_wmops(); + } +#endif + +#endif + + +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + char vq_name[1024]; + sprintf( vq_name, "SD_HRMDCT_BSL_CH%d_Nst%d", ch, stages ); /* NB starting the snr_diff() name with "SD_", will present SD-statistics for {1,2,3,4} % */ + /* test path for high rate MDCT mid channel SID quantization in the DCT domain */ +#ifdef ERI_FDCNGVQ_LOW_ROM + sprintf( vq_name, "SD_HRMDCT_NEW_CH%d_Nstages%d", ch, stages ); +#endif + snr_diff( vq_inp[ch], ms_ptr[ch], N, 0, vq_name ); + } +#endif + +#if defined( ERI_FDCNGVQ_LOW_ROM ) && defined( ERI_FDCNGVQ_LOW_ROM_TESTING ) + { + + char vq_name[1024], vq_name2[1024]; + sprintf( vq_name, "SD_HRMDCT_BSL_CH%d_Nst%d", ch, stages ); /* NB starting the name with "SD", will present SD-statistics for {1,2,3,4} % */ + + + { + sprintf( vq_name2, "msvq_encF_BSL_CH%d_%d", ch, stages ); + push_wmops( vq_name2 ); + } + + /* #0 run reference legacy HR_MDCT BSL system */ + msvq_enc( cdk_37bits_ivas_orig, NULL, NULL, vq_inp[ch], levels_37bits, FD_CNG_maxC_37bits, stages, weights, N, FD_CNG_maxN_37bits, 0 /* no DCT-search */, invTrfMatrix, indices_test[ch] ); + { + pop_wmops(); + + sprintf( vq_name2, "msvq_decF_BSL_CH%d_%d", ch, stages ); + push_wmops( vq_name2 ); + } + + msvq_dec( cdk_37bits_ivas_orig, NULL, NULL, stages, N, FD_CNG_maxN_37bits, indices_test[ch], 0 /*no DCT synt */, invTrfMatrix, vq_outp[0][ch], NULL ); + snr_diff( vq_inp[ch], vq_outp[0][ch], N, 0, vq_name ); + { + pop_wmops(); + } + } +#endif } if ( no_side_flag ) @@ -1133,6 +1346,12 @@ void FdCngEncodeMDCTStereoSID( /* pad with zeros to reach common SID frame size */ push_indice( sts[1]->hBstr, IND_ENERGY, 0, ( IVAS_SID_5k2 - 4400 ) / FRAMES_PER_SEC ); +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + pop_wmops(); + } +#endif + return; } @@ -1160,6 +1379,18 @@ void FdCngEncodeDiracMDCTStereoSID( int16_t indices[CPE_CHANNELS][FD_CNG_stages_37bits]; int16_t gain_idx[CPE_CHANNELS]; int16_t ch, p; +#ifdef ERI_FDCNGVQ_LOW_ROM + float *invTrfMatrix; + float tmpRAM[FDCNG_VQ_MAX_LEN][FDCNG_VQ_DCT_MAXTRUNC]; + float dct_target[FDCNG_VQ_DCT_MAXTRUNC]; + float tot_sig_ext[FDCNG_VQ_MAX_LEN]; + invTrfMatrix = (float *) tmpRAM; /* dynamically filled */ +#endif +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + push_wmops( "EncDiracMDCTStereoSID " ); + } +#endif /* set pointers and initialize */ for ( ch = 0; ch < CPE_CHANNELS; ch++ ) @@ -1176,7 +1407,11 @@ void FdCngEncodeDiracMDCTStereoSID( for ( ch = 0; ch < CPE_CHANNELS; ch++ ) { E[ch] = 0.0f; +#ifdef ERI_FDCNGVQ_LOW_ROM + for ( p = 0; p < NPART; p++ ) /* TBD Note: NPART should likely be N[ch] if N[ch] may change */ +#else for ( p = 0; p < NPART; p++ ) +#endif { ms_ptr[ch][p] = 10.f * log10f( lr_in_ptr[ch][p] + EPSILON ); E[ch] += ms_ptr[ch][p]; @@ -1184,12 +1419,22 @@ void FdCngEncodeDiracMDCTStereoSID( } /* M/S transform on log envelopes */ +#ifdef ERI_FDCNGVQ_LOW_ROM + convertToMS( NPART, ms_ptr[0], ms_ptr[1], 0.5f ); /* TBD Note: NPART should likely be N[0] if N[0] may change */ + + E[0] = sum_f( ms_ptr[0], NPART ); /* TBD Note: NPART should likely be N[0] if N[0] may change */ +#else convertToMS( NPART, ms_ptr[0], ms_ptr[1], 0.5f ); E[0] = sum_f( ms_ptr[0], NPART ); +#endif /* Quantize M noise shape */ +#ifdef ERI_FDCNGVQ_LOW_ROM + /* Normalize MSVQ input */ +#else /* Normalize MSVW input */ +#endif gain[0] = sum_f( ms_ptr[0] + N_GAIN_MIN, N_GAIN_MAX - N_GAIN_MIN ); gain[0] /= (float) ( N_GAIN_MAX - N_GAIN_MIN ); @@ -1199,14 +1444,38 @@ void FdCngEncodeDiracMDCTStereoSID( } /* MSVQ */ +#ifdef ERI_FDCNGVQ_LOW_ROM + /* DCT domain compressed/truncated indices used for first stage */ + /* mid quantization using stages #1 through 6 */ + if ( N[0] == FDCNG_VQ_MAX_LEN_WB ) + { + create_IDCT_N_Matrix( invTrfMatrix, N[0], FDCNG_VQ_DCT_MAXTRUNC, sizeof( tmpRAM ) / ( sizeof( float ) ) ); + /* truncated DCT 21 analysis */ + dctT2_N_apply_matrix( (const float *) ms_ptr[0], dct_target, FDCNG_VQ_DCT_MAXTRUNC, N[0], invTrfMatrix, FDCNG_VQ_DCT_MAXTRUNC, DCT_T2_21_XX ); + /* truncated IDCT21 extension to 24 synthesis */ + extend_dctN_input( ms_ptr[0], dct_target, N[0], tot_sig_ext, FDCNG_VQ_MAX_LEN, invTrfMatrix, FDCNG_VQ_DCT_MAXTRUNC, IDCT_T2_XX_21 ); /* use 18 basis vectors*/ + + mvr2r( tot_sig_ext, ms_ptr[0], FDCNG_VQ_MAX_LEN ); /* write extended result as input to VQ stage #1 */ + } + create_IDCT_N_Matrix( invTrfMatrix, FDCNG_VQ_MAX_LEN, FDCNG_VQ_DCT_MAXTRUNC, sizeof( tmpRAM ) / ( sizeof( float ) ) ); + + msvq_enc( cdk_37bits_ivas, NULL, NULL, ms_ptr[0], levels_37bits, FD_CNG_maxC_37bits, FD_CNG_stages_37bits, weights, N[0], FD_CNG_maxN_37bits, 1, invTrfMatrix, indices[0] ); + msvq_dec( cdk_37bits_ivas, NULL, NULL, FD_CNG_stages_37bits, N[0], FD_CNG_maxN_37bits, indices[0], 1, invTrfMatrix, ms_ptr[0], NULL ); + +#else msvq_enc( cdk_37bits_ivas, NULL, NULL, ms_ptr[0], levels_37bits, FD_CNG_maxC_37bits, FD_CNG_stages_37bits, weights, N[0], FD_CNG_maxN_37bits, indices[0] ); msvq_dec( cdk_37bits_ivas, NULL, NULL, FD_CNG_stages_37bits, N[0], FD_CNG_maxN_37bits, indices[0], ms_ptr[0], NULL ); +#endif /* set S to zero */ set_zero( ms_ptr[1], NPART ); /* compute M gain */ +#ifdef ERI_FDCNGVQ_LOW_ROM + gain[0] = sum_f( ms_ptr[0], NPART ); /* TBD Note: NPART should likely be N[0] if N[0] may change */ +#else gain[0] = sum_f( ms_ptr[0], NPART ); +#endif gain[0] = ( E[0] - gain[0] ) / (float) N[0]; apply_scale( &gain[0], sts[0]->hFdCngEnc->hFdCngCom->CngBandwidth, sts[0]->hDtxEnc->last_active_brate, scaleTableStereo, SIZE_SCALE_TABLE_STEREO ); @@ -1218,7 +1487,11 @@ void FdCngEncodeDiracMDCTStereoSID( gain[1] = gain[0]; /* undo M/S */ +#ifdef ERI_FDCNGVQ_LOW_ROM + convertToMS( NPART, ms_ptr[0], ms_ptr[1], 1.0f ); /* TBD Note: NPART should likely be N[0] if N[0] may change */ +#else convertToMS( NPART, ms_ptr[0], ms_ptr[1], 1.0f ); +#endif /* restore channel noise envelopes */ for ( ch = 0; ch < CPE_CHANNELS; ch++ ) @@ -1226,7 +1499,11 @@ void FdCngEncodeDiracMDCTStereoSID( HANDLE_FD_CNG_ENC hFdCngEnc = sts[ch]->hFdCngEnc; HANDLE_FD_CNG_COM hFdCngCom = hFdCngEnc->hFdCngCom; +#ifdef ERI_FDCNGVQ_LOW_ROM + for ( p = 0; p < NPART; p++ ) /* TBD Note: NPART should likely be N[0] if N[0] may change */ +#else for ( p = 0; p < NPART; p++ ) +#endif { lr_out_ptr[ch][p] = powf( 10.f, ( ms_ptr[ch][p] + gain[ch] ) / 10.f ); } @@ -1265,6 +1542,10 @@ void FdCngEncodeDiracMDCTStereoSID( } push_indice( sts[0]->hBstr, IND_ENERGY, gain_idx[0], 7 ); - +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + { + pop_wmops(); + } +#endif return; } diff --git a/lib_enc/lib_enc.c b/lib_enc/lib_enc.c index 3742dbcfdc..c41718aa40 100755 --- a/lib_enc/lib_enc.c +++ b/lib_enc/lib_enc.c @@ -703,7 +703,11 @@ static ivas_error configureEncoder( { hEncoderConfig->var_SID_rate_flag = 0; +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + if ( dtxConfig.SID_interval >= 2 && dtxConfig.SID_interval <= 100 ) +#else if ( dtxConfig.SID_interval >= 3 && dtxConfig.SID_interval <= 100 ) +#endif { hEncoderConfig->interval_SID = dtxConfig.SID_interval; } diff --git a/lib_enc/lsf_msvq_ma_enc.c b/lib_enc/lsf_msvq_ma_enc.c index a620dfac38..e221c964e7 100644 --- a/lib_enc/lsf_msvq_ma_enc.c +++ b/lib_enc/lsf_msvq_ma_enc.c @@ -48,6 +48,13 @@ #define kMaxC 8 + +#ifdef ERI_FDCNGVQ_LOW_ROM + +#include "ivas_prot.h" +void dctT2_N_apply_matrix( const float *input, float *output, const int16_t dct_dim, int16_t fdcngvq_dim, const float *idctT2_24_X_matrixQ16, const int16_t matrix_1st_dim, DCTTYPE dcttype ); +#endif + /*--------------------------------------------------------------------------* * msvq_enc() * @@ -66,7 +73,11 @@ void msvq_enc( const float w[], /* i : Weights */ const int16_t N, /* i : Vector dimension */ const int16_t maxN, /* i : Codebook dimension */ - int16_t Idx[] /* o : Indices */ +#ifdef ERI_FDCNGVQ_LOW_ROM + const int16_t applyDCT_flag, /* i : applyDCT flag */ + float *invTrfMatrix, /*i/o : synthesis matrix */ +#endif + int16_t Idx[] /* o : Indices */ ) { float *resid[2], *dist[2]; @@ -78,6 +89,44 @@ void msvq_enc( int16_t idx_buf[2 * LSFMBEST_MAX * MAX_VQ_STAGES_USED], parents[LSFMBEST_MAX]; int16_t n, maxn, start; + +#ifdef ERI_FDCNGVQ_LOW_ROM + /* buffers */ + float dct_target[FDCNG_VQ_DCT_MAXTRUNC]; + float u_mr[FDCNG_VQ_MAX_LEN]; + float u_mr_scaled[FDCNG_VQ_MAX_LEN]; + float mse_trunc_all_segms; + float mse_trunc_segm[FDCNG_VQ_DCT_NSEGM]; + float mse; + + const Word8 *cbpW8; + const Word16 *dct_col_shift_tab; + + float *st1_mse_pair; + int16_t *st1_idx_pair; + int16_t indices_st1_local[FDCNG_VQ_DCT_NSEGM * 2]; /* after stage#1 DCT search this is copied to the global indices[1][s*stages] structure */ + int16_t n_ana, p_mins[2], idx_min[2]; + DCTTYPE dcttype = DCT_T2_24_XX; + float tmp2; + + int16_t check_ind[FDCNG_VQ_DCT_NPOST]; + int16_t segm, j_full, maxC_pre; + float *st1_syn_vec_ptr; /* 8* min(n,24) floats in dynRAM */ + float *st1_mse_ptr; /* 2^¨7 == 128 floats in dRAM used for stage 1 candidate analysis, 128 Word32 in BASOP */ + float res24, high_diff[FDCNG_VQ_MAX_LEN - FDCNG_VQ_MAX_LEN_WB]; + + maxC_pre = ( FDCNG_VQ_DCT_NSEGM * 2 ); + assert( maxC <= LSFMBEST_MAX ); + assert( ( LSFMBEST_MAX * M_MAX ) > ( N * maxC ) ); + /* top of resid_buf is resid[1] and used for stage#1 residuals (input target u), + we here reuse resid[0] part of the buffer for stage#1 DCT dynamic RAM needs + */ + st1_mse_ptr = &( resid_buf[1 * LSFMBEST_MAX * M_MAX] ) - ( levels[0] ); /* reuse top of residual resid[0] scratch RAM for stage1 MSEs */ + st1_syn_vec_ptr = &( resid_buf[1 * LSFMBEST_MAX * M_MAX] ) - FDCNG_VQ_MAX_LEN * maxC; /* reuse top of resid[0] scratch RAM for residual */ + + dcttype = DCT_T2_24_XX; +#endif + /*----------------------------------------------------------------* * Allocate memory for previous (parent) and current nodes. * Parent node is indexed [0], current node is indexed [1]. @@ -159,7 +208,177 @@ void msvq_enc( { dist[1][j] = FLT_MAX; } - if ( !s ) /* means: m==1 */ + +#ifdef ERI_FDCNGVQ_LOW_ROM + if ( !s && applyDCT_flag != 0 ) /* means: m==1 */ + { /* stage 1 search in truncated dct domain without any weights */ + + n_ana = FDCNG_VQ_MAX_LEN; /* always analyze 24 values as for SWB and FB , VQ stage#1 core is using stored DCT24 coeffs */ + /*remove mean/mid fdcng stage#1 vector, in original subband domain */ + v_sub( u, cdk1r_tr_midQ_truncQ, u_mr, n_ana ); + + v_multc( u_mr, fdcng_dct_invScaleF[1], u_mr_scaled, n_ana ); /*scale up target to upscaled W8x storage domain */ + /* 16.0-->scale up from Q0 to search domain in Q4, not really needed in BASOP , impl. by shifts */ + + assert( n_ana >= FDCNG_VQ_DCT_MAXTRUNC ); /* check for WB , SWB, FB operation */ + + dctT2_N_apply_matrix( (const float *) u_mr_scaled, dct_target, min( FDCNG_VQ_DCT_MAXTRUNC, n_ana ), n_ana, invTrfMatrix, FDCNG_VQ_DCT_MAXTRUNC, dcttype ); + + mse_trunc_all_segms = 0; + mse = 0; + + /* init search state ptr's at the top */ + for ( segm = 0; segm < FDCNG_VQ_DCT_NSEGM; segm++ ) + { + /* point to a new paired location */ + st1_mse_pair = &( dist[1][2 * segm] ); /* req. ptr init +=2 */ + st1_mse_pair[0] = FLT_MAX; /* req */ + st1_mse_pair[1] = FLT_MAX; /* req */ + st1_idx_pair = &( indices_st1_local[2 * segm] ); /* +=2 */ + p_max = 0; /* req. to point to 1 or 0 */ + + /* compute segment common trunction error in dct domain */ + mse_trunc_segm[segm] = mse_trunc_all_segms; + mse_trunc_segm[segm] += sum2_f( (const float *) ( &( dct_target[cdk1_ivas_cols_per_segment[segm]] ) ), cdk1_ivas_trunc_dct_cols_per_segment[segm] ); + + cbpW8 = cdk_37bits_ivas_stage1_W8Qx_dct_sections[segm]; /* Word8 column variable Qx storage*/ + + for ( j = 0; j < cdk1_ivas_entries_per_segment[segm]; j++ ) + { + /* unweighted segmented search DCT domain loop */ + j_full = j + cdk1_ivas_cum_entries_per_segment[segm]; /* or simply use j_full++ */ + + mse = mse_trunc_segm[segm]; /* move32() init mse with with common mse truncation part */ + + dct_col_shift_tab = stage1_dct_col_syn_shift[segm]; /* ptr init */ + + for ( c2 = 0; c2 < cdk1_ivas_cols_per_segment[segm]; c2++ ) + { + +#define WMC_TOOL_SKIP + tmp = dct_target[c2] - (float) ( ( (Word16) cbpW8[c2] ) << dct_col_shift_tab[c2] ); /* Word8 storage MSE inner loop */ + LOGIC( 1 ); + SHIFT( 1 ); + ADD( 1 ); /* in BASOP: s_and(for W8->W16), shl(), sub()*/ +#undef WMC_TOOL_SKIP + + mse += tmp * tmp; /* L_mac or L_mac0() square Word16 -> Word32*/ + } + st1_mse_ptr[j_full] = mse; /* save MSe in shared dynamic 2^7=128 RAM, move32() in BASOP */ + +#define WMC_TOOL_SKIP + cbpW8 += cdk1_ivas_cols_per_segment[segm]; /* pointer increment */ +#undef WMC_TOOL_SKIP + /* overwrite with a new worst index at p_max */ + +#ifdef ERI_FDCNGVQ_LOW_ROM + /* The three inner loop if's below are not really properly instrumented by WMC tool */ + /* as a ptr to worst index will be in use, manual instrumentation to be added */ +#endif + if ( mse < st1_mse_pair[p_max] ) /* L_sub */ + { + st1_idx_pair[p_max] = j_full; /* simplified */ + } /* 2 ops */ + + if ( st1_idx_pair[p_max] == j_full ) /* simplified */ + { /*idx updated to j_full --> also update mse */ + st1_mse_pair[p_max] = mse; /* move32(), single BASOP */ + } /* 3 ops */ + /* avoid WC costly list management by always updating p_max, as we have only a pair to maintain */ + p_max = 0; /* move16() */ + if ( ( st1_mse_pair[0] - st1_mse_pair[1] ) < 0 ) /* L_sub()*/ + { + p_max = 1; /* move16() */ + } /* 3 ops ,Note 2 ops in BASOP with L_sub and L_lshr */ + + // logical shift right not available in ANSI-C + // p_max = (st1_mse_pair[0] - st1_mse_pair[1]) ">>>" 31; /* java logical shift right is >>> , in BASOP it is L_lshr */ + + /* Cost: weighted sum with cond moves ('if') => 8 in float , 7 in BASOP with L_lshr */ + } /* j in section */ + + + /* check WC optimized serial inner loop for maxC1==2 within each segment */ + + } /* next segment */ + + for ( j = 0; j < maxC_pre; j++ ) + { + // parents[j] = 0; /* preparation for stage#2 */ + /* compute_full mse using stored DCT MSE's */ + /* calculate MSE from stage1 inner using existing inner DCT domain variables */ + dist[1][j] *= fdcng_dct_scaleF[2]; /* single multiplication to get the MSE scale to the correct input domain */ + } + + p_max = maximum( dist[1], maxC_pre, NULL ); /* establish current worst candidate for stage#2 among all maxC_pre candidates */ + + p_mins[0] = minimum( dist[1], maxC_pre, NULL ); /* find best entry among all maxC_pre */ + tmp = dist[1][p_mins[0]]; + dist[1][p_mins[0]] = FLT_MAX; /* exclude */ + + p_mins[1] = minimum( dist[1], maxC_pre, NULL ); /* find 2nd best entry */ + tmp2 = dist[1][p_mins[1]]; + dist[1][p_mins[1]] = FLT_MAX; /* exclude 2nd*/ + + dist[1][p_mins[0]] = tmp; /* restore 1st */ + dist[1][p_mins[1]] = tmp2; /* restore 2nd */ + + idx_min[0] = indices_st1_local[p_mins[0]]; + idx_min[1] = indices_st1_local[p_mins[1]]; + + + /* use global exclusion list to never reselect the two (best) mse values sofar */ + st1_mse_ptr[idx_min[0]] = FLT_MAX; /* move32() */ + st1_mse_ptr[idx_min[1]] = FLT_MAX; /* move32() */ + + /* circular list of best 1-2 in use to replace some segment search candidates */ + /* using both 1st and 2nd best neigbours in fwd and rev directions */ + check_ind[0] = cdk1_ivas_segm_neighbour_fwd[idx_min[0]]; + check_ind[1] = cdk1_ivas_segm_neighbour_rev[idx_min[0]]; + + check_ind[2] = cdk1_ivas_segm_neighbour_fwd[idx_min[1]]; + check_ind[3] = cdk1_ivas_segm_neighbour_rev[idx_min[1]]; + + check_ind[4] = cdk1_ivas_segm_neighbour_fwd[check_ind[0]]; + check_ind[5] = cdk1_ivas_segm_neighbour_rev[check_ind[1]]; + + check_ind[6] = cdk1_ivas_segm_neighbour_fwd[check_ind[2]]; + check_ind[7] = cdk1_ivas_segm_neighbour_rev[check_ind[3]]; + + + for ( i = 0; i < FDCNG_VQ_DCT_NPOST; i++ ) + { + float check_mse = st1_mse_ptr[check_ind[i]] * fdcng_dct_scaleF[2]; + /* *= fdcng_dct_scaleF[2]; */ /* multiplication to get the inner outer loop scale right */ + /* est 6*8*2ops+ 8*8ops ~= 20*8 => 160 ~= 0.000128 WMOPS ! + 128 Word16 of ROM*/ + if ( check_mse < dist[1][p_max] ) + { + /* replace */ + dist[1][p_max] = check_mse; + indices_st1_local[p_max] = check_ind[i]; + st1_mse_ptr[check_ind[i]] = FLT_MAX; /* move32() */ + p_max = maximum( dist[1], maxC_pre, NULL ); /* establish a new current worst candidate among all maxC */ + } + } + + for ( c = 0; c < maxC_pre; c++ ) + { + indices[1][c * stages] = indices_st1_local[c]; /* move established stage#1 indices to global MSVQ list structure */ + } + + /* extract the selected stage one vectors in DCT domain , apply IDCT_N and scale up */ + /*always extract full length signal(24) to be able to update WB( N==21) candidate MSE values */ + for ( c = 0; c < maxC_pre; c++ ) + { + dec_FDCNG_MSVQ_stage1( indices_st1_local[c], FDCNG_VQ_MAX_LEN, invTrfMatrix, dcttype + 1, &( st1_syn_vec_ptr[c * FDCNG_VQ_MAX_LEN] ), NULL ); + } + + assert( maxC == maxC_pre ); + } + else + /* non-DCT Stage #1 code below */ +#endif + if ( !s ) /* means: m==1 */ { /* This loop is identical to the one below, except, that the inner loop over c=0..m is hardcoded to c=0, since m=1. */ @@ -202,9 +421,16 @@ void msvq_enc( } } /* if (tmp <= dist[1][p_max]) */ } /* for (j=0; j Date: Wed, 5 Apr 2023 17:59:56 +0200 Subject: [PATCH 2/6] bug fix to keep EVS bit-exactness --- lib_enc/fd_cng_enc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib_enc/fd_cng_enc.c b/lib_enc/fd_cng_enc.c index 0c83e05f8a..844eefe01c 100644 --- a/lib_enc/fd_cng_enc.c +++ b/lib_enc/fd_cng_enc.c @@ -586,8 +586,8 @@ void FdCng_encodeSID( } else { /* EVS_MONO tables */ - msvq_enc( cdk_37bits, NULL, NULL, v, levels_37bits, FD_CNG_maxC_37bits, FD_CNG_stages_37bits, w, N, FD_CNG_maxN_37bits, 1, NULL, indices ); - msvq_dec( cdk_37bits, NULL, NULL, FD_CNG_stages_37bits, N, FD_CNG_maxN_37bits, indices, 1, NULL, v, NULL ); + msvq_enc( cdk_37bits, NULL, NULL, v, levels_37bits, FD_CNG_maxC_37bits, FD_CNG_stages_37bits, w, N, FD_CNG_maxN_37bits, 0, NULL, indices ); + msvq_dec( cdk_37bits, NULL, NULL, FD_CNG_stages_37bits, N, FD_CNG_maxN_37bits, indices, 0, NULL, v, NULL ); } #else msvq_enc( codebooks, NULL, NULL, v, levels_37bits, FD_CNG_maxC_37bits, FD_CNG_stages_37bits, w, N, FD_CNG_maxN_37bits, indices ); -- GitLab From 700db0e710b7af6bffdc766440ae06f0eb56d454 Mon Sep 17 00:00:00 2001 From: Charles Kinuthia Date: Thu, 6 Apr 2023 12:49:41 +0200 Subject: [PATCH 3/6] move cdk_37bits_1_ivas table under ERI_FDCNGVQ_LOW_ROM_TESTING define --- lib_com/rom_com.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib_com/rom_com.c b/lib_com/rom_com.c index 075881cc4d..86cae7e9c9 100644 --- a/lib_com/rom_com.c +++ b/lib_com/rom_com.c @@ -6318,7 +6318,7 @@ const Word8 cdk1_ivas_segm_neighbour_rev[128] = { }; #endif - +#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING const float cdk_37bits_1_ivas[3072] = { 33.94763184f , 23.04196358f , 19.02036476f , 15.61426640f , 9.84622097f , 6.74968624f , 8.78495407f , 6.55844116f , 6.41478300f , 3.65438509f , 2.53205872f , 0.20947371f , -3.68736625f , -6.96642828f , -8.93218231f , -10.77195358f , -14.39207268f , -19.83006287f , -25.90260124f , -30.72169685f , -32.16821671f , -35.03061295f , -35.84580231f , -35.98442459f , @@ -6450,6 +6450,7 @@ const float cdk_37bits_1_ivas[3072] = 25.75157547f , 17.28746796f , 13.10127354f , 10.33002377f , 8.27671814f , 6.59895802f , 5.40835238f , 3.63577080f , 2.23206282f , 1.08383977f , -0.28453460f , -1.38477814f , -2.64369345f , -3.91356444f , -5.05506754f , -6.35320854f , -7.60085487f , -8.91501999f , -10.29950809f , -12.61900711f , -13.07838917f , -14.44057560f , -15.59240627f , -16.55293274f , 24.60115242f , 11.35327435f , 6.30881643f , 4.50763512f , 0.50214702f , -0.71103203f , 2.54261613f , -0.67276359f , -1.09342635f , 1.93361044f , 1.37798584f , 1.15170944f , 1.77881491f , -0.16942300f , -3.11068201f , -2.93669724f , -0.59286201f , 1.04607284f , 4.16106987f , 6.48291349f , 11.32464409f , 15.29464436f , 15.33285236f , 7.41661787f , }; +#endif const float cdk_37bits_1[3072] = { -- GitLab From 4df74bf35933fca68a0bc342be0a4bc109582adb Mon Sep 17 00:00:00 2001 From: Jonas Sv Date: Fri, 21 Apr 2023 17:14:43 +0200 Subject: [PATCH 4/6] cleanup of FDNCGVQ ROM OPT, builds on cygwin and msvc --- lib_com/cnst.h | 4 - lib_com/ivas_error_utils.h | 3 - lib_com/lsf_tools.c | 197 +++++++++++-------------------------- lib_com/options.h | 5 +- lib_com/prot.h | 32 +++--- lib_com/rom_com.c | 18 ++-- lib_dec/fd_cng_dec.c | 22 +---- lib_enc/dtx.c | 4 - lib_enc/fd_cng_enc.c | 138 ++------------------------ lib_enc/lib_enc.c | 4 - lib_enc/lsf_msvq_ma_enc.c | 54 +++++----- 11 files changed, 118 insertions(+), 363 deletions(-) diff --git a/lib_com/cnst.h b/lib_com/cnst.h index b4b41a7d3f..7b359e2f40 100644 --- a/lib_com/cnst.h +++ b/lib_com/cnst.h @@ -755,11 +755,7 @@ typedef enum #define STEP_SID 5.25f /* CNG & DTX - CNG energy quantization step */ #define MIN_ACT_CNG_UPD 20 /* DTX - Minimum number of consecutive active frames for CNG mode update */ -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING -#define FIXED_SID_RATE 2 /* increase DTX SID rate for better FDCNG VQ testing */ -#else #define FIXED_SID_RATE 8 /* DTX SID rate */ -#endif #define TOTALNOISE_HIST_SIZE 4 diff --git a/lib_com/ivas_error_utils.h b/lib_com/ivas_error_utils.h index b49cf309ba..b9a6b3f872 100644 --- a/lib_com/ivas_error_utils.h +++ b/lib_com/ivas_error_utils.h @@ -83,9 +83,6 @@ static inline ivas_error ivas_error_wrapper( const ivas_error error_code, const va_end( args ); fprintf( stderr, "\n\nIn function: %s(), %s:%d\n\n", function, file, line ); -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - assert( 0 ); -#endif // assert( 0 ); return error_code; diff --git a/lib_com/lsf_tools.c b/lib_com/lsf_tools.c index 06199959f2..5f0916dbd1 100644 --- a/lib_com/lsf_tools.c +++ b/lib_com/lsf_tools.c @@ -2031,10 +2031,10 @@ int16_t tcxlpc_get_cdk( void dec_FDCNG_MSVQ_stage1( int16_t j_full, /* i: index full range */ int16_t n, /* i: dimension to generate */ - const float *invTrfMatrix, /* i: matrix for synthesis */ - const DCTTYPE idcttype, /* i: specify which IDCT */ + const float *invTrfMatrix, /* i: IDCT matrix for synthesis */ + const DCTTYPE idcttype, /* i: specify which IDCT */ float *uq, /* o: synthesized stage1 vector */ - Word16 *uq_ind /* o: synthesized stage1 vector in BASOP */ + Word16 *uq_ind /* o: synthesized stage1 vector in BASOP */ ) { int16_t col, segm_ind, j; @@ -2066,22 +2066,17 @@ void dec_FDCNG_MSVQ_stage1( for ( col = 0; col < cdk1_ivas_cols_per_segment[segm_ind]; col++ ) { -#if 1 dct_vec[col] = (float) ( ( (Word16) cbpW8[col] ) << dct_col_shift_tab[col] ); -#else -#define WMC_TOOL_MAN - dct_vec[col] = (float) ( ( (Word16) cbpW8[col] ) << dct_col_shift_tab[col] ); - LOGIC( 1 ); - SHIFT( 1 ); - ADD( 1 ); /* in BASOP: s_and(for W8->W16), shl(), sub()*/ -#undef WMC_TOOL_MAN -#endif + /* LOGIC( 1 );SHIFT( 1 ); ADD( 1 ); + in BASOP: s_and(for W8->W16), shl(), sub() + */ } dctT2_N_apply_matrix( (const float *) dct_vec, idct_vec, cdk1_ivas_cols_per_segment[segm_ind], n, invTrfMatrix, FDCNG_VQ_DCT_MAXTRUNC, idcttype ); /*scale down to original fdcngvq domain and move to Q0 */ v_multc( idct_vec, fdcng_dct_scaleF[1], idct_vec, n ); - /* fdcng_dct_scaleF[1] --> 0.0625-->scale down from search Q4 domain to Q0 , not really relevant for BASOP loop */ + /* fdcng_dct_scaleF[1] --> 0.0625-->scale down from search Q4 domain to Q0 , + not really relevant for BASOP loop */ /*add common mid fdcng vector, in fdcng bands domain */ v_add( idct_vec, cdk1r_tr_midQ_truncQ, uq, n ); @@ -2107,10 +2102,10 @@ void msvq_dec( const int16_t Idx[], /* i : Indices */ #ifdef ERI_FDCNGVQ_LOW_ROM const int16_t applyIDCT_flag, /* i : applyIDCT flag */ - const float *invTrfMatrix, /* i: matrix for synthesis */ + const float *invTrfMatrix, /* i: matrix for IDCT synthesis */ #endif float *uq, /* o : quantized vector */ - Word16 *uq_ind /* o : quantized vector (fixed point) */ + Word16 *uq_ind /* o : quantized vector (fixed point) */ ) { int16_t i, n, maxn, start; @@ -2150,7 +2145,7 @@ void msvq_dec( if ( i == 0 && applyIDCT_flag != 0 ) { assert( start == 0 ); - dec_FDCNG_MSVQ_stage1( Idx[0], N, invTrfMatrix, IDCT_T2_XX_24, uq, uq_ind ); /* IDCT24 used for all synthesis */ + dec_FDCNG_MSVQ_stage1( Idx[0], N, invTrfMatrix, IDCT_T2_XX_24, uq, uq_ind ); /* IDCT_T2 N=24 used for all synthesis */ } else { @@ -2454,7 +2449,7 @@ void a2isf( /*-------------------------------------------------------------------* * dctT2_N_apply_matrix() * - * dct/idct matrix application loop for a fixed DCT basis vector length of N + * dct/idct truncated matrix appl. for DCT basis vector lengths of N *-------------------------------------------------------------------*/ void dctT2_N_apply_matrix( const float *input, @@ -2471,17 +2466,9 @@ void dctT2_N_apply_matrix( float tmp_y[FDCNG_VQ_MAX_LEN]; float *pt_y; -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - char tmp_str[1024]; - sprintf( tmp_str, "dctT2_%d_apply_mat", fdcngvq_dim ); - push_wmops( tmp_str ); - } -#endif - - /* [optionally] non-square DCT_N and IDCT_N matrix application, + /* non-square DCT_N and IDCT_N matrix application, using a stored format of an IDCT_Nx(FDCNG_VQ_DCT_MAXTRUNC) matrix */ - /* effciently parallelized in SIMD */ + /* efficiently parallelized in SIMD */ assert( dct_dim <= FDCNG_VQ_DCT_MAXTRUNC ); assert( fdcngvq_dim <= FDCNG_VQ_MAX_LEN ); @@ -2511,7 +2498,6 @@ void dctT2_N_apply_matrix( for ( i = 0; i < dim_out; i++ ) { pt_x = input; - *pt_y = 0; /* +i(DCT) or +i*maxTrunc(IDCT) */ @@ -2523,69 +2509,50 @@ void dctT2_N_apply_matrix( { #define WMC_TOOL_SKIP *pt_y += ( *pt_x++ ) * ( *pt_A ); - pt_A += mat_step_col; /* step +maxtrunc or 1 */ /* ptr indexing*/ + pt_A += mat_step_col; /* step +maxtrunc or +1 */ /* ptr indexing*/ MAC( 1 ); #undef WMC_TOOL_SKIP } pt_y++; } mvr2r( tmp_y, output, dim_out ); -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - pop_wmops(); - } -#endif } - /*-------------------------------------------------------------------* * extend_dctN_input() * * (inputN, dctN) -> idct(N_ext) idct_N matrix application loop for - * extending, extrapolating a DCT basis vector length of N to N_ext + * extending, extrapolating a DCT basis vector length of N to N_ext *-------------------------------------------------------------------*/ void extend_dctN_input( - const float *input, /* i: input in fdcng domain */ - const float *dct_input, /* i: input in dctN(fdcng) domain */ - const int16_t in_dim, /* i: in_dim==N */ - float *ext_sig, /* o: extended output in fdcng domain */ - const int16_t out_dim, /* i: output total dim */ - float *matrix, /* i: idct synthesis matrix of size N rows , n_cols columns*/ - const int16_t n_cols, /* i: number of columns == truncation length */ - DCTTYPE dcttype ) /* i: matrix operation type */ + const float *input, /* i: input in fdcng domain */ + const float *dct_input, /* i: input in dctN(fdcng) domain */ + const int16_t in_dim, /* i: in_dim == N */ + float *ext_sig, /* o: extended output in fdcng domain */ + const int16_t out_dim, /* i: output total dim */ + float *matrix, /* i: idct synthesis matrix N rows, n_cols columns */ + const int16_t n_cols, /* i: number of columns == DCT truncation length */ + DCTTYPE dcttype ) /* i: matrix operation type */ { int16_t i, j, i_rev; - const float( *ptr )[FDCNG_VQ_DCT_MAXTRUNC] = (void *) matrix; -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - char tmp_str[1024]; - sprintf( tmp_str, "extend_dct%d_input", in_dim ); - push_wmops( tmp_str ); - } -#endif - - - /* stored format of an IDCT_Nx(FDCNG_VQ_DCT_MAXTRUNC) matrix */ + /* stored format is an IDCT_Nx(FDCNG_VQ_DCT_MAXTRUNC) matrix */ assert( in_dim < FDCNG_VQ_MAX_LEN ); assert( out_dim <= FDCNG_VQ_MAX_LEN ); assert( out_dim > in_dim ); assert( n_cols == FDCNG_VQ_DCT_MAXTRUNC ); /* for *ptr[MAX_TRUNC] adressing*/ + assert( ( dcttype & 1 ) != 0 ); /* idct tables always in use for this basis vector extension */ - - assert( ( dcttype & 1 ) != 0 ); /* idct tables in use for this basis vector extension */ - - mvr2r( input, ext_sig, in_dim ); /* copy initial part, i.e. only last/tail parts are updated */ - + mvr2r( input, ext_sig, in_dim ); /* copy initial part, i.e. only last/tail parts are extended */ set_f( &( ext_sig[in_dim] ), 0.0, out_dim - in_dim ); i_rev = in_dim; /*ptr init*/ for ( i = in_dim; i < out_dim; i++ ) { /* for each extension sample */ /* i = 21 22 23; - i_rev = 20 19 18; for odd dctII simply reflect basis vector + i_rev = 20 19 18; for odd dctII reflect basis vector */ i_rev--; @@ -2593,53 +2560,41 @@ void extend_dctN_input( { /* DCTcoeff * reflected basis vector */ #define WMC_TOOL_SKIP - /* these are pure ptr operations */ + /* pure ptr MAC operations */ ext_sig[i] += dct_input[j] * ptr[i_rev][j]; /* sum up scaled and extended basis vector */ MAC( 1 ); #undef WMC_TOOL_SKIP } } -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - pop_wmops(); - } -#endif } -/* inititate idct24 FDCNG_VQ_DCT_MAXTRUNCx N matrix in RAM from a Word8+Word16 quantized compressed ROM format */ +/* inititate idct24 FDCNG_VQ_DCT_MAXTRUNCx N matrix in RAM from a quantized compressed ROM format */ void create_IDCT_N_Matrix( float *inv_matrixFloatQ, const int16_t N, const int16_t n_cols, const int16_t alloc_size ) { int16_t c, c1, r, r_flip, W16_val; - int16_t len; /* <=FDCNG_VQ_MAX_LEN */ + int16_t len; int16_t mat_cpy_size; - const Word16 *val_ptr; + const Word16 *absval_ptr; const Word8 *idx_ptr; - int8_t idx; -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - char tmp_str[1024]; - sprintf( tmp_str, "create_IDCT_%d_mat", N ); - push_wmops( tmp_str ); - } -#endif - + Word16 idx; + float( *ptr )[FDCNG_VQ_DCT_MAXTRUNC] = (void *) inv_matrixFloatQ; /* fixed number of columns pointers, to simplifies adressing in ANSIC */ - val_ptr = unique_idctT2_24coeffsQ16; + absval_ptr = unique_idctT2_24coeffsQ16; idx_ptr = idctT2_24_compressed_idx; len = FDCNG_VQ_MAX_LEN; + if ( N == FDCNG_VQ_MAX_LEN_WB ) { - val_ptr = unique_idctT2_21coeffsQ16; + absval_ptr = unique_idctT2_21coeffsQ16; idx_ptr = idctT2_21_compressed_idx; len = N; } assert( alloc_size >= ( n_cols * len ) ); /* enough space for the full expanded IDCT matrix */ assert( N <= len ); - W16_val = 0; /* safety init */ - mat_cpy_size = ( n_cols ) * ( len / 2 ); /* one integer division of "len" */ + mat_cpy_size = ( n_cols ) * ( len >> 1 ); /* NB integer division of "len" */ if ( ( len & 1 ) != 0 ) { /* odd sized DCT with a non-reflected center row */ @@ -2648,75 +2603,37 @@ void create_IDCT_N_Matrix( float *inv_matrixFloatQ, const int16_t N, const int16 for ( c = 0; c < mat_cpy_size; c++ ) { - idx = idx_ptr[c]; - if ( idx >= 0 ) - { - W16_val = ( val_ptr[idx] ); - } + idx = (Word16) ( idx_ptr[c] ); + W16_val = absval_ptr[abs( idx )]; + if ( idx < 0 ) { - W16_val = -( val_ptr[-idx] ); + W16_val = -( W16_val ); } - inv_matrixFloatQ[c] = ( +1.52587890625e-05f ) * ( (float) W16_val ); /* 1.0/2.^16 scaling to a float-"Q0" scaling not done in BASOP */ + inv_matrixFloatQ[c] = ( +1.52587890625e-05f ) * ( (float) W16_val ); /* 1.0/2.^16 scaling to a float-"Q0" , a scaling that is not done in BASOP */ } - { /* a temporary local scope for matrix ptr's */ - /* for even number of coeffs DCT24, - flip symmetry for odd, even used to save 50% further Table ROM */ - /* for odd DCT center is not flipped e.g DCT21 */ - /* float inv_matrixFloatQ[len][FDCNG_VQ_DCT_MAXTRUNC]; */ + /* for even number of coeffs DCT24, + flip symmetry for odd, even is used to save 50% IDCT Table ROM */ + /* for an odd DCT center is not flipped e.g for DCT21 */ - /* use fixed number of columns pointers , to simplify adressing code below */ - float( *ptr )[FDCNG_VQ_DCT_MAXTRUNC] = (void *) inv_matrixFloatQ; - float( *ptr21 )[FDCNG_VQ_MAX_LEN_WB] = (void *) inv_matrixFloatQ; + assert( n_cols == FDCNG_VQ_DCT_MAXTRUNC ); + assert( ( n_cols & 1 ) == 0 ); - if ( n_cols == FDCNG_VQ_DCT_MAXTRUNC ) - { - - assert( ( n_cols & 1 ) == 0 ); - for ( c = 0; c < ( n_cols ); c += 2 ) - { - c1 = c + 1; - r_flip = len - 1; - for ( r = 0; r < ( len / 2 ); r++, r_flip-- ) - { -#define WMC_TOOL_SKIP - /* pure ptr based calculations */ - ptr[r_flip][c] = ptr[r][c]; /* flipped */ - ptr[r_flip][c1] = -ptr[r][c1]; /* flipped and sign swapped */ - - MOVE( 2 ); - MULT( 1 ); /*for negate */ -#undef WMC_TOOL_SKIP - } - } - } - else + for ( c = 0; c < ( n_cols ); c += 2 ) + { + c1 = c + 1; + r_flip = len - 1; + for ( r = 0; r < ( len / 2 ); r++, r_flip-- ) { - float sign_swap = 1.0f; - assert( n_cols == FDCNG_VQ_MAX_LEN_WB ); - for ( c = 0; c < ( n_cols ); c++ ) - { - r_flip = len - 1; - sign_swap = 1.0f - 2.0f * ( c & 1 ); /*signsawpp odd columns */ - for ( r = 0; r < ( len / 2 ); r++, r_flip-- ) - { #define WMC_TOOL_SKIP - /* pure ptr based calculations */ - ptr21[r_flip][c] = sign_swap * ptr21[r][c]; /* flipped and potetially sign swapped */ - - MULT( 1 ); - MOVE( 1 ); + ptr[r_flip][c] = ptr[r][c]; /* flipped */ + ptr[r_flip][c1] = -( ptr[r][c1] ); /* flipped and sign swapped */ + MOVE( 2 ); + MULT( 1 ); /* for negate */ #undef WMC_TOOL_SKIP - } - } } } -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - pop_wmops(); - } -#endif } diff --git a/lib_com/options.h b/lib_com/options.h index 66d1ed90d0..feb9a4038b 100644 --- a/lib_com/options.h +++ b/lib_com/options.h @@ -83,7 +83,7 @@ /*#define ALLOW_BYTE_EP*/ /* allow byte fer pattern files and check fer pattern file validity */ #define WRAP_AS_EIDXOR /* wraps FER file (as in STL_eid-xor.c/softbit.c) */ -#define DEBUG_FORCE_MDCT_STEREO_MODE /* Force stereo mode decision for MDCT stereo: -stere 3 1 forces L/R coding and -stereo 3 2 forces full M/S coding */ +#define DEBUG_FORCE_MDCT_STEREO_MODE /* Force stereo mode decision for MDCT stereo: -stereo 3 1 forces L/R coding and -stereo 3 2 forces full M/S coding */ /*#define DEBUG_STEREO_DFT_NOCORE*/ /* DFT stereo: by-pass core coder at decoder side*/ /*#define DEBUG_STEREO_DFT_NOSTEREO*/ /* DFT stereo: by-pass stereo processing at encoder and decoder side*/ /*#define DEBUG_STEREO_DFT_NOQRES*/ @@ -174,8 +174,7 @@ -#define ERI_FDCNGVQ_LOW_ROM /* Eri: ~1.6kW Table ROM saving for IVAS FDCNG-VQ */ -/*# define ERI_FDCNGVQ_LOW_ROM_TESTING */ /* Enable testing vs. Baseline for XC SD-measurements , deactivate for WMOPS measurement */ +#define ERI_FDCNGVQ_LOW_ROM /* Eri: Contribution #31 Table ROM saving for IVAS FDCNG-VQ modes */ /* ################## End DEVELOPMENT switches ######################### */ /* clang-format on */ diff --git a/lib_com/prot.h b/lib_com/prot.h index d73c6e98de..f330ce50d0 100644 --- a/lib_com/prot.h +++ b/lib_com/prot.h @@ -8103,34 +8103,32 @@ void dec_FDCNG_MSVQ_stage1( Word16 *uq_ind /* o: synthesized stage1 vector in BASOP */ ); - void create_IDCT_N_Matrix( - float *inv_matrixFloatQ, /*i/o: RAM buffer */ - const int16_t N, /* i: DCT length , number of time samples */ - const int16_t n_cols, /*i: number of dct coeffs (as DCt may be truncated */ - - const int16_t alloc_size /*i: RAM buffer size in elements*/ + float *inv_matrixFloatQ, /* i/o: RAM buffer */ + const int16_t N, /* i: DCT length , number of time samples */ + const int16_t n_cols, /* i: number of dct coeffs (as DCT may be truncated) */ + const int16_t alloc_size /* i: RAM buffer size in elements*/ ); void dctT2_N_apply_matrix( - const float *input, - float *output, - const int16_t dct_dim, - int16_t fdcngvq_dim, - const float *idctT2_N_16matrixQ16, - const int16_t matrix_1st_dim, - DCTTYPE dcttype ); + const float *input, /* i: input in fdcng or DCT(fdcng) domain */ + float *output, /* o: output in DCT(fdcng) or fdcng ordomain */ + const int16_t dct_dim, /* i: dct processing dim possibly truncated */ + int16_t fdcngvq_dim, /* i: fdcng domain length */ + const float *idctT2_N_16matrixQ16, /* i: IDCT matrix */ + const int16_t matrix_1st_dim, /* i: */ + DCTTYPE dcttype ); /* i: matrix operation type */ void extend_dctN_input( - const float *input, /* i: input in fdcng domain */ - const float *dct_input, /* i: input in dctN(fdcng) domain */ - const int16_t in_dim, /* i: in_dim==N */ + const float *input, /* i: input in fdcng domain */ + const float *dct_input, /* i: input in dctN(fdcng) domain */ + const int16_t in_dim, /* i: in_dim==N */ float *ext_sig, /* o: extended output in fdcng domain */ const int16_t out_dim, /* i: output total dim */ float *matrix, /* i: idct matrix of size N rows , n_cols columns*/ const int16_t n_cols, /* i: number of columns == truncation length */ - DCTTYPE dcttype ); /* i: matrix operation type */ + DCTTYPE dcttype ); /* i: matrix type */ #endif void PulseResynchronization( diff --git a/lib_com/rom_com.c b/lib_com/rom_com.c index 86cae7e9c9..6701d39534 100644 --- a/lib_com/rom_com.c +++ b/lib_com/rom_com.c @@ -6037,7 +6037,16 @@ const int16_t levels_37bits[FD_CNG_stages_37bits] = { 128, 64, 64, 64, 64, 64 }; const int16_t bits_37bits[FD_CNG_stages_37bits] = { 7, 6, 6, 6, 6, 6 }; #ifdef ERI_FDCNGVQ_LOW_ROM -/* IDCT_MATRIX_ROM: */ +/* IDCT_MATRIX_ROM: 18*24 Word16 = 432 Word16 */ +/* or compressed IDCT_MATRIX_ROM: 18*24 Word8 + 25 = 230 Word16 + WMOPS (INDIRECT(432) and STORE(432) ) */ + +/* Stage1 Word8 tables 16x8+ 17*10+ 17*16 + 78*18 = = 1974 Word8 -> 987 Word16 */ + +/* ROM storeSizeW8 = W8reduction (3072- (987+230) )/3072 = 1207/3072 --> 39.3 % */ +/* ROM with DCTII-24 in PROM = W8reduction (3072- (987) )/3072 = /3072 --> 31.8 % */ + +/* additional minor Table ROM ( dct_mid points 18 Word16, dct_col_upshifts 52, scaleFactors 2*2 = ~= 74 Word16s */ + const Word16 cdk1_ivas_entries_per_segment[FDCNG_VQ_DCT_NSEGM] = { 16, 17, 17, 78 }; const Word16 cdk1_ivas_cum_entries_per_segment[FDCNG_VQ_DCT_NSEGM + 1] = { 0, 16 ,33, 50, 128 }; @@ -6318,7 +6327,8 @@ const Word8 cdk1_ivas_segm_neighbour_rev[128] = { }; #endif -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING + +#ifndef ERI_FDCNGVQ_LOW_ROM const float cdk_37bits_1_ivas[3072] = { 33.94763184f , 23.04196358f , 19.02036476f , 15.61426640f , 9.84622097f , 6.74968624f , 8.78495407f , 6.55844116f , 6.41478300f , 3.65438509f , 2.53205872f , 0.20947371f , -3.68736625f , -6.96642828f , -8.93218231f , -10.77195358f , -14.39207268f , -19.83006287f , -25.90260124f , -30.72169685f , -32.16821671f , -35.03061295f , -35.84580231f , -35.98442459f , @@ -6926,10 +6936,6 @@ const float cdk_37bits_6[1536] = const float * const cdk_37bits[] = { cdk_37bits_1, cdk_37bits_2, cdk_37bits_3, cdk_37bits_4, cdk_37bits_5, cdk_37bits_6 }; -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING -const float * const cdk_37bits_ivas_orig[] = { cdk_37bits_1_ivas, cdk_37bits_2, cdk_37bits_3, cdk_37bits_4, cdk_37bits_5, cdk_37bits_6 }; -#endif - #ifdef ERI_FDCNGVQ_LOW_ROM const float * const cdk_37bits_ivas[] = { NULL, cdk_37bits_2, cdk_37bits_3, cdk_37bits_4, cdk_37bits_5, cdk_37bits_6 }; #else diff --git a/lib_dec/fd_cng_dec.c b/lib_dec/fd_cng_dec.c index 871b9bd09b..71b3dbad7f 100644 --- a/lib_dec/fd_cng_dec.c +++ b/lib_dec/fd_cng_dec.c @@ -2033,11 +2033,6 @@ void FdCngDecodeMDCTStereoSID( float tmpRAM[FDCNG_VQ_MAX_LEN][FDCNG_VQ_DCT_MAXTRUNC]; #endif -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - push_wmops( "DecodeMDCTStereoSID" ); - } -#endif #ifdef ERI_FDCNGVQ_LOW_ROM invTrfMatrix = (float *) tmpRAM; @@ -2127,11 +2122,6 @@ void FdCngDecodeMDCTStereoSID( } } -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - pop_wmops(); - } -#endif return; } @@ -2139,7 +2129,7 @@ void FdCngDecodeMDCTStereoSID( /*------------------------------------------------------------------- * FdCngDecodeDiracMDCTStereoSID() * - * Decode FD-Cng parameters for CNG in 2TC DirAC mode from the bitstream + * Decode FD-CNG parameters for CNG in 2TC DirAC mode from the bitstream *-------------------------------------------------------------------*/ void FdCngDecodeDiracMDCTStereoSID( @@ -2159,11 +2149,6 @@ void FdCngDecodeDiracMDCTStereoSID( float tmpRAM[FDCNG_VQ_MAX_LEN][FDCNG_VQ_DCT_MAXTRUNC]; #endif -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - push_wmops( "DecDiracMDCTStereoSID" ); - } -#endif #ifdef ERI_FDCNGVQ_LOW_ROM invTrfMatrix = (float *) tmpRAM; /* dynamically filled */ @@ -2234,10 +2219,5 @@ void FdCngDecodeDiracMDCTStereoSID( } } -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - pop_wmops(); - } -#endif return; } diff --git a/lib_enc/dtx.c b/lib_enc/dtx.c index 40caf46d58..c99a8faf28 100644 --- a/lib_enc/dtx.c +++ b/lib_enc/dtx.c @@ -281,11 +281,7 @@ void dtx( } else { -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - hDtxEnc->max_SID = FIXED_SID_RATE; -#else hDtxEnc->max_SID = 3; -#endif } if ( hDtxEnc->max_SID > hDtxEnc->interval_SID ) diff --git a/lib_enc/fd_cng_enc.c b/lib_enc/fd_cng_enc.c index 844eefe01c..e00d010b9e 100644 --- a/lib_enc/fd_cng_enc.c +++ b/lib_enc/fd_cng_enc.c @@ -39,10 +39,6 @@ #include "options.h" #ifdef DEBUGGING #include "debug.h" -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING -#include -#include -#endif #endif #include #include "rom_enc.h" @@ -526,11 +522,6 @@ void FdCng_encodeSID( const float *const *codebooks = ( st->element_mode == EVS_MONO ) ? cdk_37bits : cdk_37bits_ivas; #endif const float gain_q_offset = ( st->element_mode == EVS_MONO ) ? GAIN_Q_OFFSET_EVS : GAIN_Q_OFFSET_IVAS; -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - push_wmops( "FdCng_encodeSID" ); - } -#endif /* Init */ N = hFdCngEnc->npartDec; @@ -569,14 +560,16 @@ void FdCng_encodeSID( if ( st->element_mode != EVS_MONO ) { /* DCT domain compressed/truncated indices used for first stage */ - /* quantization with stage 1 in DCT24 domain, stages 2 through 6 directly in FDCNG band domain */ + /* quantization with stage1 stored in DCT24 domain, stages 2 through 6 directly dearched + in FDCNG band domain + */ if ( N == FDCNG_VQ_MAX_LEN_WB ) { create_IDCT_N_Matrix( invTrfMatrix, N, FDCNG_VQ_DCT_MAXTRUNC, sizeof( tmpRAM ) / ( sizeof( float ) ) ); - /* truncated DCT 21 analysis */ + /* truncated DCT21 analysis */ dctT2_N_apply_matrix( (const float *) v, dct_target, FDCNG_VQ_DCT_MAXTRUNC, N, invTrfMatrix, FDCNG_VQ_DCT_MAXTRUNC, DCT_T2_21_XX ); - /* truncated IDCT21 extension to 24 synthesis */ - extend_dctN_input( v, dct_target, N, tot_sig_ext, FDCNG_VQ_MAX_LEN, invTrfMatrix, FDCNG_VQ_DCT_MAXTRUNC, IDCT_T2_XX_21 ); /* use 18 basis vectors*/ + /* truncated IDCT21 extension to 24 bands */ + extend_dctN_input( v, dct_target, N, tot_sig_ext, FDCNG_VQ_MAX_LEN, invTrfMatrix, FDCNG_VQ_DCT_MAXTRUNC, IDCT_T2_XX_21 ); mvr2r( tot_sig_ext, v, FDCNG_VQ_MAX_LEN ); /* write extended result as input to VQ stage #1 */ } @@ -678,11 +671,6 @@ void FdCng_encodeSID( lpc_from_spectrum( hFdCngCom, hFdCngEnc->startBandDec, hFdCngEnc->stopFFTbinDec, preemph_fac ); -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - pop_wmops(); - } -#endif return; } @@ -1026,11 +1014,6 @@ void FdCngEncodeMDCTStereoSID( int16_t no_side_flag; int16_t is_inp_ms; -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - float vq_inp[CPE_CHANNELS][NPART]; - float vq_outp[4][CPE_CHANNELS][NPART]; /* XC test several VQ results */ - int16_t indices_test[CPE_CHANNELS][FD_CNG_stages_37bits]; -#endif #ifdef ERI_FDCNGVQ_LOW_ROM float tot_sig_ext[FDCNG_VQ_MAX_LEN], dct_target[CPE_CHANNELS][FDCNG_VQ_DCT_MAXTRUNC]; /* 24 +2*18*/ float *invTrfMatrix; @@ -1038,11 +1021,6 @@ void FdCngEncodeMDCTStereoSID( invTrfMatrix = (float *) tmpRAM; /* dynamically filled */ #endif -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - push_wmops( "EncMDCTStereoSID" ); - } -#endif is_inp_ms = 0; if ( hCPE->hCoreCoder[0]->cng_sba_flag == 1 ) @@ -1109,9 +1087,6 @@ void FdCngEncodeMDCTStereoSID( for ( p = 0; p < N; p++ ) { ms_ptr[ch][p] -= gain[ch]; -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - vq_inp[ch][p] = ms_ptr[ch][p]; -#endif } #ifdef ERI_FDCNGVQ_LOW_ROM @@ -1139,9 +1114,6 @@ void FdCngEncodeMDCTStereoSID( extend_dctN_input( ms_ptr[ch], dct_target[ch], N, tot_sig_ext, FDCNG_VQ_MAX_LEN, invTrfMatrix /* DCT_N basis vectors */, FDCNG_VQ_DCT_MAXTRUNC, IDCT_T2_XX_21 ); /* use 18 basis vectors*/ mvr2r( tot_sig_ext, ms_ptr[ch], FDCNG_VQ_MAX_LEN ); /* write extended result as input to VQ */ -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - mvr2r( ms_ptr[ch], vq_inp[ch], FDCNG_VQ_MAX_LEN ); -#endif } } create_IDCT_N_Matrix( invTrfMatrix, FDCNG_VQ_MAX_LEN, FDCNG_VQ_DCT_MAXTRUNC, sizeof( tmpRAM ) / ( sizeof( float ) ) ); /*always create/set up IDCT24 matrix in RAM */ @@ -1168,98 +1140,15 @@ void FdCngEncodeMDCTStereoSID( { #define FDCNG_STAGE1VQ_USE_DCT 1 -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - char vq_name[1024]; - sprintf( vq_name, "msvq_encF_NEW_CH%d_%d", ch, stages ); - push_wmops( vq_name ); - } -#endif - msvq_enc( cdk_37bits_ivas, NULL, NULL, ms_ptr[ch], levels_37bits, FD_CNG_maxC_37bits, stages, weights, N, FD_CNG_maxN_37bits, FDCNG_STAGE1VQ_USE_DCT, invTrfMatrix, indices[ch] ); -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - pop_wmops(); - char vq_name[1024]; - sprintf( vq_name, "msvq_decF_NEW_CH%d_%d", ch, stages ); - push_wmops( vq_name ); - } -#endif msvq_dec( cdk_37bits_ivas, NULL, NULL, stages, N, FD_CNG_maxN_37bits, indices[ch], FDCNG_STAGE1VQ_USE_DCT, invTrfMatrix, ms_ptr[ch], NULL ); -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - pop_wmops(); - } -#endif } #else -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - char vq_name[1024]; - sprintf( vq_name, "msvq_encF_BSL_CH%d_%d", ch, stages ); - push_wmops( vq_name ); - } -#endif msvq_enc( cdk_37bits_ivas, NULL, NULL, ms_ptr[ch], levels_37bits, FD_CNG_maxC_37bits, stages, weights, N, FD_CNG_maxN_37bits, indices[ch] ); -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - pop_wmops(); - char vq_name[1024]; - sprintf( vq_name, "msvq_decF_BSL_CH%d_%d", ch, stages ); - push_wmops( vq_name ); - } -#endif msvq_dec( cdk_37bits_ivas, NULL, NULL, stages, N, FD_CNG_maxN_37bits, indices[ch], ms_ptr[ch], NULL ); -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - pop_wmops(); - } -#endif -#endif - - -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - char vq_name[1024]; - sprintf( vq_name, "SD_HRMDCT_BSL_CH%d_Nst%d", ch, stages ); /* NB starting the snr_diff() name with "SD_", will present SD-statistics for {1,2,3,4} % */ - /* test path for high rate MDCT mid channel SID quantization in the DCT domain */ -#ifdef ERI_FDCNGVQ_LOW_ROM - sprintf( vq_name, "SD_HRMDCT_NEW_CH%d_Nstages%d", ch, stages ); -#endif - snr_diff( vq_inp[ch], ms_ptr[ch], N, 0, vq_name ); - } -#endif - -#if defined( ERI_FDCNGVQ_LOW_ROM ) && defined( ERI_FDCNGVQ_LOW_ROM_TESTING ) - { - - char vq_name[1024], vq_name2[1024]; - sprintf( vq_name, "SD_HRMDCT_BSL_CH%d_Nst%d", ch, stages ); /* NB starting the name with "SD", will present SD-statistics for {1,2,3,4} % */ - - - { - sprintf( vq_name2, "msvq_encF_BSL_CH%d_%d", ch, stages ); - push_wmops( vq_name2 ); - } - - /* #0 run reference legacy HR_MDCT BSL system */ - msvq_enc( cdk_37bits_ivas_orig, NULL, NULL, vq_inp[ch], levels_37bits, FD_CNG_maxC_37bits, stages, weights, N, FD_CNG_maxN_37bits, 0 /* no DCT-search */, invTrfMatrix, indices_test[ch] ); - { - pop_wmops(); - - sprintf( vq_name2, "msvq_decF_BSL_CH%d_%d", ch, stages ); - push_wmops( vq_name2 ); - } - - msvq_dec( cdk_37bits_ivas_orig, NULL, NULL, stages, N, FD_CNG_maxN_37bits, indices_test[ch], 0 /*no DCT synt */, invTrfMatrix, vq_outp[0][ch], NULL ); - snr_diff( vq_inp[ch], vq_outp[0][ch], N, 0, vq_name ); - { - pop_wmops(); - } - } #endif } @@ -1346,11 +1235,6 @@ void FdCngEncodeMDCTStereoSID( /* pad with zeros to reach common SID frame size */ push_indice( sts[1]->hBstr, IND_ENERGY, 0, ( IVAS_SID_5k2 - 4400 ) / FRAMES_PER_SEC ); -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - pop_wmops(); - } -#endif return; } @@ -1386,11 +1270,6 @@ void FdCngEncodeDiracMDCTStereoSID( float tot_sig_ext[FDCNG_VQ_MAX_LEN]; invTrfMatrix = (float *) tmpRAM; /* dynamically filled */ #endif -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - push_wmops( "EncDiracMDCTStereoSID " ); - } -#endif /* set pointers and initialize */ for ( ch = 0; ch < CPE_CHANNELS; ch++ ) @@ -1542,10 +1421,5 @@ void FdCngEncodeDiracMDCTStereoSID( } push_indice( sts[0]->hBstr, IND_ENERGY, gain_idx[0], 7 ); -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - { - pop_wmops(); - } -#endif return; } diff --git a/lib_enc/lib_enc.c b/lib_enc/lib_enc.c index 7f723b7f83..d9bd9d688f 100644 --- a/lib_enc/lib_enc.c +++ b/lib_enc/lib_enc.c @@ -706,11 +706,7 @@ static ivas_error configureEncoder( { hEncoderConfig->var_SID_rate_flag = 0; -#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING - if ( dtxConfig.SID_interval >= 2 && dtxConfig.SID_interval <= 100 ) -#else if ( dtxConfig.SID_interval >= 3 && dtxConfig.SID_interval <= 100 ) -#endif { hEncoderConfig->interval_SID = dtxConfig.SID_interval; } diff --git a/lib_enc/lsf_msvq_ma_enc.c b/lib_enc/lsf_msvq_ma_enc.c index e221c964e7..f68b40cb68 100644 --- a/lib_enc/lsf_msvq_ma_enc.c +++ b/lib_enc/lsf_msvq_ma_enc.c @@ -74,8 +74,8 @@ void msvq_enc( const int16_t N, /* i : Vector dimension */ const int16_t maxN, /* i : Codebook dimension */ #ifdef ERI_FDCNGVQ_LOW_ROM - const int16_t applyDCT_flag, /* i : applyDCT flag */ - float *invTrfMatrix, /*i/o : synthesis matrix */ + const int16_t applyDCT_flag, /* i : applyDCT flag */ + float *invTrfMatrix, /*i/o : synthesis matrix */ #endif int16_t Idx[] /* o : Indices */ ) @@ -111,8 +111,8 @@ void msvq_enc( int16_t check_ind[FDCNG_VQ_DCT_NPOST]; int16_t segm, j_full, maxC_pre; - float *st1_syn_vec_ptr; /* 8* min(n,24) floats in dynRAM */ - float *st1_mse_ptr; /* 2^¨7 == 128 floats in dRAM used for stage 1 candidate analysis, 128 Word32 in BASOP */ + float *st1_syn_vec_ptr; /* 8* 24 floats in dynRAM */ + float *st1_mse_ptr; /* 2^¨7 == 128 floats in existing dRAM used for stage 1 candidate analysis, 128 Word32 in BASOP */ float res24, high_diff[FDCNG_VQ_MAX_LEN - FDCNG_VQ_MAX_LEN_WB]; maxC_pre = ( FDCNG_VQ_DCT_NSEGM * 2 ); @@ -128,7 +128,7 @@ void msvq_enc( #endif /*----------------------------------------------------------------* - * Allocate memory for previous (parent) and current nodes. + * Allocate memory for previous (parent) and current nodes. * Parent node is indexed [0], current node is indexed [1]. *----------------------------------------------------------------*/ @@ -213,7 +213,7 @@ void msvq_enc( if ( !s && applyDCT_flag != 0 ) /* means: m==1 */ { /* stage 1 search in truncated dct domain without any weights */ - n_ana = FDCNG_VQ_MAX_LEN; /* always analyze 24 values as for SWB and FB , VQ stage#1 core is using stored DCT24 coeffs */ + n_ana = FDCNG_VQ_MAX_LEN; /* VQ stage#1 core is always using stored DCT24 coeffs */ /*remove mean/mid fdcng stage#1 vector, in original subband domain */ v_sub( u, cdk1r_tr_midQ_truncQ, u_mr, n_ana ); @@ -264,7 +264,7 @@ void msvq_enc( mse += tmp * tmp; /* L_mac or L_mac0() square Word16 -> Word32*/ } - st1_mse_ptr[j_full] = mse; /* save MSe in shared dynamic 2^7=128 RAM, move32() in BASOP */ + st1_mse_ptr[j_full] = mse; /* save MSE in shared dynamic 2^7=128 RAM, move32() in BASOP */ #define WMC_TOOL_SKIP cbpW8 += cdk1_ivas_cols_per_segment[segm]; /* pointer increment */ @@ -273,39 +273,36 @@ void msvq_enc( #ifdef ERI_FDCNGVQ_LOW_ROM /* The three inner loop if's below are not really properly instrumented by WMC tool */ - /* as a ptr to worst index will be in use, manual instrumentation to be added */ + /* a ptr to worst index will be in use */ #endif if ( mse < st1_mse_pair[p_max] ) /* L_sub */ { st1_idx_pair[p_max] = j_full; /* simplified */ - } /* 2 ops */ + } /* BASOP 2 ops */ if ( st1_idx_pair[p_max] == j_full ) /* simplified */ { /*idx updated to j_full --> also update mse */ st1_mse_pair[p_max] = mse; /* move32(), single BASOP */ - } /* 3 ops */ + } /* BASOP 3 ops */ /* avoid WC costly list management by always updating p_max, as we have only a pair to maintain */ p_max = 0; /* move16() */ if ( ( st1_mse_pair[0] - st1_mse_pair[1] ) < 0 ) /* L_sub()*/ { p_max = 1; /* move16() */ - } /* 3 ops ,Note 2 ops in BASOP with L_sub and L_lshr */ + } /* BASOP 3 ops ,Note 2 ops possible in BASOP with L_sub and L_lshr */ - // logical shift right not available in ANSI-C - // p_max = (st1_mse_pair[0] - st1_mse_pair[1]) ">>>" 31; /* java logical shift right is >>> , in BASOP it is L_lshr */ + /* Note: logical shift right not available in ANSI-C */ + /* p_max = (st1_mse_pair[0] - st1_mse_pair[1]) ">>>" 31; */ + /* in java logical shift right is available as >>> , in BASOP it is L_lshr */ /* Cost: weighted sum with cond moves ('if') => 8 in float , 7 in BASOP with L_lshr */ } /* j in section */ - - /* check WC optimized serial inner loop for maxC1==2 within each segment */ - } /* next segment */ for ( j = 0; j < maxC_pre; j++ ) { - // parents[j] = 0; /* preparation for stage#2 */ - /* compute_full mse using stored DCT MSE's */ + /* compute_full mse using stored DCT24 domain MSE's */ /* calculate MSE from stage1 inner using existing inner DCT domain variables */ dist[1][j] *= fdcng_dct_scaleF[2]; /* single multiplication to get the MSE scale to the correct input domain */ } @@ -314,7 +311,7 @@ void msvq_enc( p_mins[0] = minimum( dist[1], maxC_pre, NULL ); /* find best entry among all maxC_pre */ tmp = dist[1][p_mins[0]]; - dist[1][p_mins[0]] = FLT_MAX; /* exclude */ + dist[1][p_mins[0]] = FLT_MAX; /* exclude 1st */ p_mins[1] = minimum( dist[1], maxC_pre, NULL ); /* find 2nd best entry */ tmp2 = dist[1][p_mins[1]]; @@ -331,8 +328,8 @@ void msvq_enc( st1_mse_ptr[idx_min[0]] = FLT_MAX; /* move32() */ st1_mse_ptr[idx_min[1]] = FLT_MAX; /* move32() */ - /* circular list of best 1-2 in use to replace some segment search candidates */ - /* using both 1st and 2nd best neigbours in fwd and rev directions */ + /* circular MSE-neigbour list in use to potentially replace some segment search candidates */ + /* using both 1st and 2nd best neighbours in fwd and rev directions */ check_ind[0] = cdk1_ivas_segm_neighbour_fwd[idx_min[0]]; check_ind[1] = cdk1_ivas_segm_neighbour_rev[idx_min[0]]; @@ -345,18 +342,17 @@ void msvq_enc( check_ind[6] = cdk1_ivas_segm_neighbour_fwd[check_ind[2]]; check_ind[7] = cdk1_ivas_segm_neighbour_rev[check_ind[3]]; - for ( i = 0; i < FDCNG_VQ_DCT_NPOST; i++ ) { float check_mse = st1_mse_ptr[check_ind[i]] * fdcng_dct_scaleF[2]; - /* *= fdcng_dct_scaleF[2]; */ /* multiplication to get the inner outer loop scale right */ - /* est 6*8*2ops+ 8*8ops ~= 20*8 => 160 ~= 0.000128 WMOPS ! + 128 Word16 of ROM*/ + /* *= fdcng_dct_scaleF[2]; */ /* multiplication in use to get the float outer loop scale correct */ + if ( check_mse < dist[1][p_max] ) { - /* replace */ + /* new winner , replace */ dist[1][p_max] = check_mse; indices_st1_local[p_max] = check_ind[i]; - st1_mse_ptr[check_ind[i]] = FLT_MAX; /* move32() */ + st1_mse_ptr[check_ind[i]] = FLT_MAX; /* BASOP: move32() */ p_max = maximum( dist[1], maxC_pre, NULL ); /* establish a new current worst candidate among all maxC */ } } @@ -514,8 +510,8 @@ void msvq_enc( #ifdef ERI_FDCNGVQ_LOW_ROM /* recalc MSE for WB(0..20) coeffs , - essentially subtract res21^2 ,res22^2, res23^2 that was included in stage1 MSE in the DCT24 domain truncated search - , excludes the waveform contributions at pos 21,22,23 to the MSE, important to keep MSEs update for the subsequent stages + essentially subtract res21^2 ,res22^2, res23^2 that was included in stage1 MSE in the DCT24 domain truncated search, + excludes the waveform contributions at pos 21,22,23 to the MSE, important to keep WB MSEs update for the subsequent stages */ if ( s == 0 && applyDCT_flag != 0 && n == FDCNG_VQ_MAX_LEN_WB ) { @@ -529,7 +525,7 @@ void msvq_enc( dist[1][c] -= res24; /* remove DCT24 high band error contribution */ } - /* update p_max, as it may potentially change, due to the core DCT24 search optimizing over longer basis vectors than 21 */ + /* update p_max, as it may potentially change, due to the core DCT24 search originally optimizing over longer basis vectors than 21 */ p_max = maximum( dist[1], maxC, NULL ); } #endif -- GitLab From 0feda3009e3c4819a705a3786eb372ea4fc712ad Mon Sep 17 00:00:00 2001 From: Jonas Sv Date: Tue, 25 Apr 2023 14:19:43 +0200 Subject: [PATCH 5/6] clang format fix --- lib_dec/ivas_sns_dec.c | 4 ++-- lib_enc/ivas_sns_enc.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/lib_dec/ivas_sns_dec.c b/lib_dec/ivas_sns_dec.c index e23c22e9fc..4c8840dcb7 100644 --- a/lib_dec/ivas_sns_dec.c +++ b/lib_dec/ivas_sns_dec.c @@ -284,7 +284,7 @@ void dequantize_sns( nStages = SNS_MSVQ_NSTAGES_SIDE; means = ( st->core == TCX_20_CORE ) ? ivas_sns_means_side_tcx20 : ivas_sns_means_side_tcx10; #ifdef ERI_FDCNGVQ_LOW_ROM - msvq_dec( side_cdbks, NULL, NULL, nStages, M, M, &indices[ch][idxIndices + SNS_STEREO_MODE_OFFSET_INDICES],0, NULL, snsQ, NULL ); + msvq_dec( side_cdbks, NULL, NULL, nStages, M, M, &indices[ch][idxIndices + SNS_STEREO_MODE_OFFSET_INDICES], 0, NULL, snsQ, NULL ); #else msvq_dec( side_cdbks, NULL, NULL, nStages, M, M, &indices[ch][idxIndices + SNS_STEREO_MODE_OFFSET_INDICES], snsQ, NULL ); #endif @@ -294,7 +294,7 @@ void dequantize_sns( else { #ifdef ERI_FDCNGVQ_LOW_ROM - msvq_dec( cdbks, NULL, NULL, nStages, M, M, &indices[ch][idxIndices + SNS_STEREO_MODE_OFFSET_INDICES], 0, NULL, snsQ, NULL ); + msvq_dec( cdbks, NULL, NULL, nStages, M, M, &indices[ch][idxIndices + SNS_STEREO_MODE_OFFSET_INDICES], 0, NULL, snsQ, NULL ); #else msvq_dec( cdbks, NULL, NULL, nStages, M, M, &indices[ch][idxIndices + SNS_STEREO_MODE_OFFSET_INDICES], snsQ, NULL ); #endif diff --git a/lib_enc/ivas_sns_enc.c b/lib_enc/ivas_sns_enc.c index 7badaa5204..1c8fc063a2 100644 --- a/lib_enc/ivas_sns_enc.c +++ b/lib_enc/ivas_sns_enc.c @@ -484,9 +484,9 @@ int16_t quantize_sns( v_sub( sns_ptr, means, snsQ, M ); #ifdef ERI_FDCNGVQ_LOW_ROM msvq_enc( side_cdbks, NULL, NULL, snsQ, side_levels, 3, nStages, weights, M, M, 0, NULL, &indices[idxIndices] ); - msvq_dec( side_cdbks, NULL, NULL, nStages, M, M, &indices[idxIndices],0, NULL, snsQ, NULL ); + msvq_dec( side_cdbks, NULL, NULL, nStages, M, M, &indices[idxIndices],0, NULL, snsQ, NULL ); #else - msvq_enc( side_cdbks, NULL, NULL, snsQ, side_levels, 3, nStages, weights, M, M, &indices[idxIndices] ); + msvq_enc( side_cdbks, NULL, NULL, snsQ, side_levels, 3, nStages, weights, M, M, &indices[idxIndices] ); msvq_dec( side_cdbks, NULL, NULL, nStages, M, M, &indices[idxIndices], snsQ, NULL ); #endif v_add( snsQ, means, snsQ, M ); @@ -497,7 +497,7 @@ int16_t quantize_sns( msvq_enc( cdbks, NULL, NULL, sns_ptr, levels, 3, nStages, weights, M, M, 0, NULL, &indices[idxIndices] ); msvq_dec( cdbks, NULL, NULL, nStages, M, M, &indices[idxIndices], 0, NULL, snsQ, NULL ); #else - msvq_enc( cdbks, NULL, NULL, sns_ptr, levels, 3, nStages, weights, M, M, &indices[idxIndices] ); + msvq_enc( cdbks, NULL, NULL, sns_ptr, levels, 3, nStages, weights, M, M, &indices[idxIndices] ); msvq_dec( cdbks, NULL, NULL, nStages, M, M, &indices[idxIndices], snsQ, NULL ); #endif } -- GitLab From c75fe3b69b9ef98ef09119bfbcf034c19bf4e977 Mon Sep 17 00:00:00 2001 From: Jonas Sv Date: Tue, 25 Apr 2023 16:13:43 +0200 Subject: [PATCH 6/6] clang format fix2 --- lib_dec/ivas_sns_dec.c | 2 -- lib_enc/ivas_sns_enc.c | 6 +++--- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/lib_dec/ivas_sns_dec.c b/lib_dec/ivas_sns_dec.c index 4c8840dcb7..6cf80ec0d1 100644 --- a/lib_dec/ivas_sns_dec.c +++ b/lib_dec/ivas_sns_dec.c @@ -298,8 +298,6 @@ void dequantize_sns( #else msvq_dec( cdbks, NULL, NULL, nStages, M, M, &indices[ch][idxIndices + SNS_STEREO_MODE_OFFSET_INDICES], snsQ, NULL ); #endif - - } idxIndices += nStages; } diff --git a/lib_enc/ivas_sns_enc.c b/lib_enc/ivas_sns_enc.c index 1c8fc063a2..762b0aeb0f 100644 --- a/lib_enc/ivas_sns_enc.c +++ b/lib_enc/ivas_sns_enc.c @@ -484,11 +484,11 @@ int16_t quantize_sns( v_sub( sns_ptr, means, snsQ, M ); #ifdef ERI_FDCNGVQ_LOW_ROM msvq_enc( side_cdbks, NULL, NULL, snsQ, side_levels, 3, nStages, weights, M, M, 0, NULL, &indices[idxIndices] ); - msvq_dec( side_cdbks, NULL, NULL, nStages, M, M, &indices[idxIndices],0, NULL, snsQ, NULL ); + msvq_dec( side_cdbks, NULL, NULL, nStages, M, M, &indices[idxIndices], 0, NULL, snsQ, NULL ); #else msvq_enc( side_cdbks, NULL, NULL, snsQ, side_levels, 3, nStages, weights, M, M, &indices[idxIndices] ); msvq_dec( side_cdbks, NULL, NULL, nStages, M, M, &indices[idxIndices], snsQ, NULL ); -#endif +#endif v_add( snsQ, means, snsQ, M ); } else @@ -499,7 +499,7 @@ int16_t quantize_sns( #else msvq_enc( cdbks, NULL, NULL, sns_ptr, levels, 3, nStages, weights, M, M, &indices[idxIndices] ); msvq_dec( cdbks, NULL, NULL, nStages, M, M, &indices[idxIndices], snsQ, NULL ); -#endif +#endif } idxIndices += nStages; -- GitLab