Commit 20fdf6dd authored by Archit Tamarapu's avatar Archit Tamarapu
Browse files

Merge branch '107-jbm2fer-processing-bugs-introduced-with-174' into 'main' 

Resolve "JBM2FER processing bugs introduced with !174"

See merge request !200
parents 595887f2 b2671b4e

ivas_processing_scripts/processing/ivas.py

+5 −5
Original line number Diff line number Diff line
@@ -256,11 +256,11 @@ class IVAS(Processing): 
                delay_profile = self.tx["error_pattern"]

                len_pattern = length_pattern(delay_profile)



                if not self.tx.get("errpat_late_loss_rate") and not self.tx.get(

                    "delay"

                if not self.tx.get("errpatt_late_loss_rate") and not self.tx.get(

                    "errpatt_delay"

                ):

                    raise KeyError(

                        "Either errpat_late_loss_rate or errpat_delay must be specified for converting a delay error profile to an error profile!"

                        f"Either errpatt_late_loss_rate or errpat_delay must be specified for converting a delay error profile to an error profile!\nGenerating {bitstream_processed}"

                    )



                errpat = bitstream.with_name(
@@ -275,9 +275,9 @@ class IVAS(Processing): 
                )

                dlyerr_2_errpat(

                    delay_profile,

                    delay=self.tx.get("errpat_delay"),

                    delay=self.tx.get("errpatt_delay"),

                    fer_pattern=errpat,

                    late_loss_rate=self.tx.get("errpat_late_loss_rate"),

                    late_loss_rate=self.tx.get("errpatt_late_loss_rate"),

                    shift=shift,

                )

                eid_xor(errpat, bitstream, bitstream_processed)

ivas_processing_scripts/processing/tx.py

+8 −12
Original line number Diff line number Diff line
@@ -50,26 +50,22 @@ def get_tx_cfg(cfg: TestConfig, cond_cfg: dict, is_EVS: bool = False) -> Optiona 
    if tx_cfg_tmp.get("type", None) == "FER":

        tx_cfg = {

            "type": tx_cfg_tmp.get("type"),

            "error_pattern": get_abs_path(tx_cfg_tmp.get("error_pattern", None)),

            "error_rate": tx_cfg_tmp.get("error_rate", None),

            "error_pattern": get_abs_path(tx_cfg_tmp.get("error_pattern")),

            "error_rate": tx_cfg_tmp.get("error_rate"),

            "master_seed": cfg.master_seed,

            "prerun_seed": cfg.prerun_seed,

        }

    elif tx_cfg_tmp.get("type", None).startswith("JBM"):

        tx_cfg = {

            "type": tx_cfg_tmp.get("type"),

            "error_pattern": get_abs_path(tx_cfg_tmp.get("error_pattern", None)),

            "errpatt_seed": tx_cfg_tmp.get("errpatt_seed", None),

            "error_profile": tx_cfg_tmp.get("error_profile", None),

            "n_frames_per_packet": tx_cfg_tmp.get("n_frames_per_packet", None),

            "error_pattern": get_abs_path(tx_cfg_tmp.get("error_pattern")),

            "errpatt_seed": tx_cfg_tmp.get("errpatt_seed"),

            "error_profile": tx_cfg_tmp.get("error_profile"),

            "n_frames_per_packet": tx_cfg_tmp.get("n_frames_per_packet"),

            "master_seed": cfg.master_seed,

            "errpatt_late_loss_rate": tx_cfg_tmp.get("errpatt_late_loss_rate"),

            "errpatt_delay": tx_cfg_tmp.get("errpatt_delay"),

        }

        # EVS specific keys

        if is_EVS:

            tx_cfg["errpatt_late_loss_rate"] = tx_cfg_tmp.get(

                "errpatt_late_loss_rate", None

            )

            tx_cfg["errpatt_delay"] = tx_cfg_tmp.get("errpatt_delay", None)

    else:

        raise ValueError("Type of bitstream procesing either missing or not valid")