Loading lib_dec/ivas_mdct_core_dec_fx.c +7 −1 Original line number Diff line number Diff line Loading @@ -1266,7 +1266,7 @@ void ivas_mdct_core_reconstruct_fx( /* Note: these buffers are not subframe-based, hence no indexing with k */ set16_fx( &st->hHQ_core->old_out_LB_fx[0], 0, L_frame[ch] ); set16_fx( &st->hHQ_core->old_out_fx[0], 0, L_frameTCX[ch] ); #ifdef FIX_1348_BIT_PRECISION_IMPROVEMENT_DYNAMIC_QOLD_NO #ifdef FIX_1348_BIT_PRECISION_IMPROVEMENT_DYNAMIC_QOLD st->hHQ_core->Q_old_wtda = Q15; st->hHQ_core->Q_old_wtda_LB = Q15; #endif Loading Loading @@ -1390,6 +1390,7 @@ void ivas_mdct_core_reconstruct_fx( ELSE /*ACELP core for ACELP-PLC */ { #ifdef FIX_1348_BIT_PRECISION_IMPROVEMENT_QWIN #if 0 Copy( st->hTcxDec->old_synth, synth_buf_fx, st->hTcxDec->old_synth_len ); // Q = st->hTcxDec->q_old_synth Copy_Scale_sig( st->hTcxDec->old_synthFB_fx, synth_bufFB_fx, st->hTcxDec->old_synth_lenFB, sub( st->hTcxDec->q_old_synth, st->Q_syn ) ); // Q = st->hTcxDec->q_old_synth Loading @@ -1397,6 +1398,11 @@ void ivas_mdct_core_reconstruct_fx( // Scale_sig( synth_bufFB_fx, st->hTcxDec->old_synth_lenFB, -2 ); // Scale_sig( synth_bufFB_fx, st->hTcxDec->old_synth_lenFB, +2 ); /////////////////////////////////////////////////////////////////////////////////// #else Copy_Scale_sig( st->hTcxDec->old_synth, synth_buf_fx, st->hTcxDec->old_synth_len, sub( 0, st->hTcxDec->q_old_synth ) ); // Q = st->hTcxDec->q_old_synth -> Q0 Copy_Scale_sig( st->hTcxDec->old_synthFB_fx, synth_bufFB_fx, st->hTcxDec->old_synth_lenFB, sub( 0, st->Q_syn ) ); // Q = st->hTcxDec->q_old_synth -> Q0 q_syn = 0; #endif #endif assert( EQ_16( st->bfi, 1 ) ); /* PLC: [TCX: TD PLC] */ Loading Loading
lib_dec/ivas_mdct_core_dec_fx.c +7 −1 Original line number Diff line number Diff line Loading @@ -1266,7 +1266,7 @@ void ivas_mdct_core_reconstruct_fx( /* Note: these buffers are not subframe-based, hence no indexing with k */ set16_fx( &st->hHQ_core->old_out_LB_fx[0], 0, L_frame[ch] ); set16_fx( &st->hHQ_core->old_out_fx[0], 0, L_frameTCX[ch] ); #ifdef FIX_1348_BIT_PRECISION_IMPROVEMENT_DYNAMIC_QOLD_NO #ifdef FIX_1348_BIT_PRECISION_IMPROVEMENT_DYNAMIC_QOLD st->hHQ_core->Q_old_wtda = Q15; st->hHQ_core->Q_old_wtda_LB = Q15; #endif Loading Loading @@ -1390,6 +1390,7 @@ void ivas_mdct_core_reconstruct_fx( ELSE /*ACELP core for ACELP-PLC */ { #ifdef FIX_1348_BIT_PRECISION_IMPROVEMENT_QWIN #if 0 Copy( st->hTcxDec->old_synth, synth_buf_fx, st->hTcxDec->old_synth_len ); // Q = st->hTcxDec->q_old_synth Copy_Scale_sig( st->hTcxDec->old_synthFB_fx, synth_bufFB_fx, st->hTcxDec->old_synth_lenFB, sub( st->hTcxDec->q_old_synth, st->Q_syn ) ); // Q = st->hTcxDec->q_old_synth Loading @@ -1397,6 +1398,11 @@ void ivas_mdct_core_reconstruct_fx( // Scale_sig( synth_bufFB_fx, st->hTcxDec->old_synth_lenFB, -2 ); // Scale_sig( synth_bufFB_fx, st->hTcxDec->old_synth_lenFB, +2 ); /////////////////////////////////////////////////////////////////////////////////// #else Copy_Scale_sig( st->hTcxDec->old_synth, synth_buf_fx, st->hTcxDec->old_synth_len, sub( 0, st->hTcxDec->q_old_synth ) ); // Q = st->hTcxDec->q_old_synth -> Q0 Copy_Scale_sig( st->hTcxDec->old_synthFB_fx, synth_bufFB_fx, st->hTcxDec->old_synth_lenFB, sub( 0, st->Q_syn ) ); // Q = st->hTcxDec->q_old_synth -> Q0 q_syn = 0; #endif #endif assert( EQ_16( st->bfi, 1 ) ); /* PLC: [TCX: TD PLC] */ Loading