Commit 61355038 authored by Sandesh Venkatesh's avatar Sandesh Venkatesh
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Merge branch '3gpp_issue_927_fix' into 'main' 

Fix for 3GPP issue 927: Audible artifacts for LFE with PLC for 5.1 MCT at 96kbps [allow regression]

See merge request !668
parents abf44ea6 6c7169ec

lib_dec/ivas_lfe_plc_fx.c

+10 −6
Original line number Diff line number Diff line
@@ -1327,12 +1327,16 @@ void ivas_lfe_tdplc_fx( 


    set16_fx( mem_fx, 0, 2 * LFE_PLC_FDEL / LFE_PLC_DSF );



    Copy_Scale_sig_32_16( prevsynth_fx, prevsynth_16_fx, LFE_PLC_BUFLEN, -16 ); // Q5 = Q21 - Q16

    Copy_Scale_sig_32_16( rec_frame_fx, rec_frame_16_fx, LFE_PLC_RECLEN, 0 );   // Q5

    Copy_Scale_sig_32_16( prevsynth_fx, prevsynth_16_fx, LFE_PLC_BUFLEN, -prevsynth_q_fx ); // Q0

    Copy_Scale_sig_32_16( rec_frame_fx, rec_frame_16_fx, LFE_PLC_RECLEN, -Q5 );             // Q0



    Word16 Q_new_inp, mem_decim_size, size_modified;

    size_modified = modify_Fs_ivas_fx( prevsynth_16_fx + LFE_PLC_BUFLEN - LFE_PLC_FDEL / LFE_PLC_DSF, LFE_PLC_FDEL / LFE_PLC_DSF, LFE_PLC_FS, rec_frame_us_16_fx, 48000, mem_fx, 0, &Q_new_inp, &mem_decim_size );

    Scale_sig( rec_frame_us_16_fx, size_modified, negate( Q_new_inp ) ); /* scaling back to Q0 */



    size_modified = modify_Fs_ivas_fx( rec_frame_16_fx, LFE_PLC_RECLEN, LFE_PLC_FS, rec_frame_us_16_fx, 48000, mem_fx, 0, &Q_new_inp, &mem_decim_size );

    Scale_sig( rec_frame_us_16_fx, size_modified, negate( Q_new_inp ) ); /* scaling back to Q0 */



    Word16 Q_new_inp, mem_decim_size; // TO be removed

    modify_Fs_fx( prevsynth_16_fx + LFE_PLC_BUFLEN - LFE_PLC_FDEL / LFE_PLC_DSF, LFE_PLC_FDEL / LFE_PLC_DSF, LFE_PLC_FS, rec_frame_us_16_fx, 48000, mem_fx, 0, &Q_new_inp, &mem_decim_size );

    modify_Fs_fx( rec_frame_16_fx, LFE_PLC_RECLEN, LFE_PLC_FS, rec_frame_us_16_fx, 48000, mem_fx, 0, &Q_new_inp, &mem_decim_size );

    /*samples are generated with 48k sampling rate

    and then converted to required sampling rate by simple decimation

    as signal is already bandlimited*/
@@ -1349,7 +1353,7 @@ void ivas_lfe_tdplc_fx( 
        }

    }



    Copy_Scale_sig_16_32( rec_frame_us_16_fx, rec_frame_us_fx, LFE_PLC_RECLEN_48K, 5 ); // Q10 = rec_frame_q + 5

    Copy_Scale_sig_16_32( rec_frame_us_16_fx, rec_frame_us_fx, LFE_PLC_RECLEN_48K, 10 ); // Q10 = rec_frame_q + 5



    FOR( i = 0; i < 2; i++ )

    {