Commit c3878f42 authored by multrus's avatar multrus
Browse files

[cleanup] accept NONBE_1214_PLC_LSF_MEMORY

parent ec3e611e

lib_com/options.h

+0 −1
Original line number Diff line number Diff line
@@ -159,7 +159,6 @@ 
#define FIX_1129_EXT_REND_OUTPUT_HIGH                   /* Philips: issue 1129: External renderer BINAURAL_ROOM_REVERB format output level too high compared to internal rendering output */

#define NONBE_1244_FIX_SWB_BWE_MEMORY                   /* VA: issue 1244: fix to SWB BWE memory in case of switching from FB coding - pending a review by Huawei */

#define FIX_1113_CLDFB_REND_IN_ISAR                     /* issue 1113: fix the use of CLDFB renderer in split-rendering at the external renderer */

#define NONBE_1214_PLC_LSF_MEMORY                       /* VA: issue 1224: reset ACELP PLC FEC memory in case of switching from MDCT stereo to TD/DFT stereo */

#define NONBE_1293_SR_HRTF                              /* VA: issue 1293: add support of external HRTFs in split rendering */

#define FIX_1249_REMOVE_OBSOLETE_ALLRAD_MATRIX          /* VA: issue 1249: remove obsolete code around ALLRAD decoder matrix */

#define NONBE_1220_OMASA_JBM_BRATE_SW_FLUSH             /* VA: issue 1220: fix bug in renderer flush in OMASA 1ISM JBM bitrate switching */

lib_dec/core_switching_dec.c

+0 −5
Original line number Diff line number Diff line
@@ -263,14 +263,9 @@ ivas_error core_switching_pre_dec( 
        st->uv_count = 0;

    }



#ifdef NONBE_1214_PLC_LSF_MEMORY

    if ( ( ( st->core == ACELP_CORE || st->core == AMR_WB_CORE ) && st->last_core == HQ_CORE ) /* EVS and HQ -> ACELP */ ||

         ( ( st->element_mode == IVAS_CPE_DFT || st->element_mode == IVAS_CPE_TD || ( st->element_mode == IVAS_CPE_MDCT && last_element_mode == IVAS_CPE_DFT ) ) && nchan_out == 2 && st->core_brate != SID_2k40 && st->core_brate != FRAME_NO_DATA && ( last_core_brate_st0 == FRAME_NO_DATA || last_core_brate_st0 == SID_2k40 ) ) ||

         ( st->core == ACELP_CORE && st->last_L_frame > L_FRAME16k ) /* TCX @ 25.6/32 kHz -> ACELP */ )

#else

    if ( ( ( st->core == ACELP_CORE || st->core == AMR_WB_CORE ) && st->last_core == HQ_CORE ) || ( ( st->element_mode == IVAS_CPE_DFT || st->element_mode == IVAS_CPE_TD || ( st->element_mode == IVAS_CPE_MDCT && last_element_mode == IVAS_CPE_DFT ) ) && nchan_out == 2 &&

                                                                                                    st->core_brate != SID_2k40 && st->core_brate != FRAME_NO_DATA && ( last_core_brate_st0 == FRAME_NO_DATA || last_core_brate_st0 == SID_2k40 ) ) )

#endif

    {

        if ( st->element_mode == IVAS_CPE_DFT || st->element_mode == IVAS_CPE_TD )

        {

lib_enc/core_switching_enc.c

+0 −4
Original line number Diff line number Diff line
@@ -171,13 +171,9 @@ void core_switching_pre_enc( 
        st->uv_count = 0;

    }



#ifdef NONBE_1214_PLC_LSF_MEMORY

    if ( ( ( st->core == ACELP_CORE || st->core == AMR_WB_CORE ) && st->last_core == HQ_CORE ) /* EVS and HQ -> ACELP */ ||

         ( ( st->element_mode == IVAS_CPE_DFT || st->element_mode == IVAS_CPE_TD || ( st->element_mode == IVAS_CPE_MDCT && last_element_mode == IVAS_CPE_DFT ) ) && active_cnt == 1 ) ||

         ( st->core == ACELP_CORE && st->last_L_frame > L_FRAME16k ) /* TCX @ 25.6/32 kHz -> ACELP */ )

#else

    if ( ( ( st->core == ACELP_CORE || st->core == AMR_WB_CORE ) && st->last_core == HQ_CORE ) || ( ( st->element_mode == IVAS_CPE_DFT || st->element_mode == IVAS_CPE_TD || ( st->element_mode == IVAS_CPE_MDCT && last_element_mode == IVAS_CPE_DFT ) ) && active_cnt == 1 ) )

#endif

    {

        /* Reset the ACELP core in case of HQ->ACELP core switching */