Loading lib_com/options.h +0 −1 Original line number Diff line number Diff line Loading @@ -94,7 +94,6 @@ /* #################### Start NON-BE switches ############################ */ /* any switch which is non-be wrt. TS 26.251 V3.0 */ #define FIX_2432_ISM_SPIKES_16KHZ /* VA: basop issue 2432: fix spikes in ISM decoding at 16kHz output sampling rate */ #define FIX_2448_RENDERER_MSAN_ERROR /* FhG: basop issue 2448: fix MSAN error with MSA rendering */ #define FIX_2283_ISM_MD_DELAY /* Dolby: Fix ISM metadata delay round-off */ #define FIX_2283_Q_CLDFB /* FhG: Fix Q format issue in CLDFB */ Loading lib_dec/ivas_core_dec_fx.c +0 −4 Original line number Diff line number Diff line Loading @@ -1035,14 +1035,10 @@ ivas_error ivas_core_dec_fx( test(); test(); test(); #ifdef FIX_2432_ISM_SPIKES_16KHZ test(); test(); test(); IF( ( st->core == ACELP_CORE && ( EQ_16( st->extl, -1 ) || EQ_16( st->extl, SWB_CNG ) || ( EQ_16( st->extl, WB_BWE ) && st->bws_cnt > 0 && flag_swb_tbe == 0 ) ) ) && flag_bwe_bws == 0 ) #else IF( ( st->core == ACELP_CORE && ( EQ_16( st->extl, -1 ) || EQ_16( st->extl, SWB_CNG ) ) ) && flag_bwe_bws == 0 ) #endif { set32_fx( hb_synth_32_fx[n], 0, L_FRAME48k ); } Loading Loading
lib_com/options.h +0 −1 Original line number Diff line number Diff line Loading @@ -94,7 +94,6 @@ /* #################### Start NON-BE switches ############################ */ /* any switch which is non-be wrt. TS 26.251 V3.0 */ #define FIX_2432_ISM_SPIKES_16KHZ /* VA: basop issue 2432: fix spikes in ISM decoding at 16kHz output sampling rate */ #define FIX_2448_RENDERER_MSAN_ERROR /* FhG: basop issue 2448: fix MSAN error with MSA rendering */ #define FIX_2283_ISM_MD_DELAY /* Dolby: Fix ISM metadata delay round-off */ #define FIX_2283_Q_CLDFB /* FhG: Fix Q format issue in CLDFB */ Loading
lib_dec/ivas_core_dec_fx.c +0 −4 Original line number Diff line number Diff line Loading @@ -1035,14 +1035,10 @@ ivas_error ivas_core_dec_fx( test(); test(); test(); #ifdef FIX_2432_ISM_SPIKES_16KHZ test(); test(); test(); IF( ( st->core == ACELP_CORE && ( EQ_16( st->extl, -1 ) || EQ_16( st->extl, SWB_CNG ) || ( EQ_16( st->extl, WB_BWE ) && st->bws_cnt > 0 && flag_swb_tbe == 0 ) ) ) && flag_bwe_bws == 0 ) #else IF( ( st->core == ACELP_CORE && ( EQ_16( st->extl, -1 ) || EQ_16( st->extl, SWB_CNG ) ) ) && flag_bwe_bws == 0 ) #endif { set32_fx( hb_synth_32_fx[n], 0, L_FRAME48k ); } Loading