Loading lib_dec/er_dec_tcx_fx.c +0 −4 Original line number Diff line number Diff line Loading @@ -950,10 +950,6 @@ void con_tcx_fx( hTcxDec->Q_syn_Overl_TDAC = hTcxDec->Q_syn_Overl_TDACFB; move16(); lerp( st->hHQ_core->old_out_fx, st->hHQ_core->old_out_LB_fx, st->L_frame, L_frame ); #ifdef FIX_1348_BIT_PRECISION_IMPROVEMENT_NO hHQ_core->Q_old_wtda_LB = hHQ_core->Q_old_wtda; move16(); #endif st->old_enr_LP = Enr_1_Az_fx( A_local, L_SUBFR ); /*Q3*/ move16(); Loading lib_dec/ivas_mdct_core_dec_fx.c +0 −3 Original line number Diff line number Diff line Loading @@ -1282,9 +1282,6 @@ void ivas_mdct_core_reconstruct_fx( { Scale_sig( st->mem_syn2_fx, M, sub( st->Q_syn, add( q_win, 2 ) ) ); // q_win+2 -> st->Q_syn: in this case, E_UTIL_f_preemph2 shifts st->mem_syn2_fx by 2 bits } #ifdef FIX_1348_BIT_PRECISION_IMPROVEMENT_DYNAMIC_QOLD_NO Scale_sig( st->mem_syn2_fx, M, sub( st->Q_syn, q_win ) ); // q_win -> Q_syn #endif } ELSE /*ACELP core for ACELP-PLC */ { Loading Loading
lib_dec/er_dec_tcx_fx.c +0 −4 Original line number Diff line number Diff line Loading @@ -950,10 +950,6 @@ void con_tcx_fx( hTcxDec->Q_syn_Overl_TDAC = hTcxDec->Q_syn_Overl_TDACFB; move16(); lerp( st->hHQ_core->old_out_fx, st->hHQ_core->old_out_LB_fx, st->L_frame, L_frame ); #ifdef FIX_1348_BIT_PRECISION_IMPROVEMENT_NO hHQ_core->Q_old_wtda_LB = hHQ_core->Q_old_wtda; move16(); #endif st->old_enr_LP = Enr_1_Az_fx( A_local, L_SUBFR ); /*Q3*/ move16(); Loading
lib_dec/ivas_mdct_core_dec_fx.c +0 −3 Original line number Diff line number Diff line Loading @@ -1282,9 +1282,6 @@ void ivas_mdct_core_reconstruct_fx( { Scale_sig( st->mem_syn2_fx, M, sub( st->Q_syn, add( q_win, 2 ) ) ); // q_win+2 -> st->Q_syn: in this case, E_UTIL_f_preemph2 shifts st->mem_syn2_fx by 2 bits } #ifdef FIX_1348_BIT_PRECISION_IMPROVEMENT_DYNAMIC_QOLD_NO Scale_sig( st->mem_syn2_fx, M, sub( st->Q_syn, q_win ) ); // q_win -> Q_syn #endif } ELSE /*ACELP core for ACELP-PLC */ { Loading