Commit f9caa3f4 authored by Jan Kiene's avatar Jan Kiene
Browse files

Merge branch 'update-main-pc-with-main' into 'main-pc' 

[skip-name-check][non-BE][renderer-non-BE][allow-regression][split-non-BE]Update main-pc with main

See merge request !1303
parents 27353653 28596529

.gitlab-ci.yml

+5 −2
Original line number Diff line number Diff line
@@ -752,6 +752,10 @@ stages: 
  script:

    - *print-common-info



    # create empty files for all artifacts to suppress warnings in case of no regressions found or all is BE

    - touch $XML_REPORT_BRANCH $XML_REPORT_MAIN $HTML_REPORT_BRANCH $HTML_REPORT_MAIN $CSV_BRANCH $CSV_MAIN $SUMMARY_HTML_ARTIFACT_NAME $FLOAT_REF_COMMIT_FILE $CUT_COMMIT_FILE $MERGE_TARGET_COMMIT_FILE regressions_crashes.csv regressions_MLD.csv regressions_MAXIMUM_ABS_DIFF.csv regressions_MIN_SSNR.csv regressions_MIN_ODG.csv improvements_crashes.csv improvements_MLD.csv improvements_MAXIMUM_ABS_DIFF.csv improvements_MIN_SSNR.csv improvements_MIN_ODG.csv

    - mkdir $IMAGES_ARTIFACT_NAME



    - set -euxo pipefail



    - if [ -s $FAILED_TESTCASES_LIST ]; then
@@ -797,7 +801,6 @@ stages: 
    - mv tests/dut tests/dut_branch



    # create the summary based on the branch

    - mkdir $IMAGES_ARTIFACT_NAME

    - for MEASURE in MLD DIFF SSNR ODG;do python3 scripts/create_histogram_summary.py $CSV_BRANCH $IMAGES_ARTIFACT_NAME/summary_"$MEASURE".csv $IMAGES_ARTIFACT_NAME/summary_"$MEASURE".png --measure $MEASURE; done

    - python3 ci/basop-pages/create_summary_page.py $SUMMARY_HTML_ARTIFACT_NAME $CI_JOB_ID $CI_JOB_NAME
@@ -899,7 +902,7 @@ stages: 
    - set -euxo pipefail

    - make_args="CLANG=$CLANG_NUM"

    - if [[ $CLANG_NUM == 3 ]]; then

    -   export UBSAN_OPTIONS="suppressions=scripts/ubsan_basop.supp,report_error_type=1"

    -   export UBSAN_OPTIONS="suppressions=scripts/ubsan_basop.supp,report_error_type=1,print_stacktrace=1"

    -   python3 scripts/basop_create_ignorelist_for_ubsan.py

    -   make_args="$make_args IGNORELIST=1"

    - fi

Workspace_msvc/lib_com.vcxproj

+0 −2
Original line number Diff line number Diff line
@@ -279,7 +279,6 @@ 
    <ClCompile Include="..\lib_com\swb_bwe_com_fx.c" />

    <ClCompile Include="..\lib_com\swb_bwe_com_hr_fx.c" />

    <ClCompile Include="..\lib_com\swb_bwe_com_lr_fx.c" />

    <ClCompile Include="..\lib_com\swb_tbe_com.c" />

    <ClCompile Include="..\lib_com\swb_tbe_com_fx.c" />

    <ClCompile Include="..\lib_com\syn_12k8_fx.c" />

    <ClCompile Include="..\lib_com\syn_filt_fx.c" />
@@ -321,7 +320,6 @@ 
    <ClInclude Include="..\lib_com\ivas_cnst.h" />

    <ClInclude Include="..\lib_com\ivas_error.h" />

    <ClInclude Include="..\lib_com\ivas_error_utils.h" />

    <ClInclude Include="..\lib_com\ivas_prot.h" />

    <ClInclude Include="..\lib_com\ivas_prot_fx.h" />

    <ClInclude Include="..\lib_com\ivas_rom_com.h" />

    <ClInclude Include="..\lib_com\ivas_rom_com_fx.h" />

Workspace_msvc/lib_com.vcxproj.filters

+1 −7
Original line number Diff line number Diff line
@@ -430,9 +430,6 @@ 
    <ClCompile Include="..\lib_com\rom_com.c">

      <Filter>common_all_c</Filter>

    </ClCompile>

    <ClCompile Include="..\lib_com\swb_tbe_com.c">

      <Filter>common_all_c</Filter>

    </ClCompile>

    <ClCompile Include="..\lib_com\tcx_mdct_window.c">

      <Filter>common_all_c</Filter>

    </ClCompile>
@@ -575,9 +572,6 @@ 
    <ClInclude Include="..\lib_com\ivas_error_utils.h">

      <Filter>common_h</Filter>

    </ClInclude>

    <ClInclude Include="..\lib_com\ivas_prot.h">

      <Filter>common_h</Filter>

    </ClInclude>

    <ClInclude Include="..\lib_com\ivas_rom_com.h">

      <Filter>common_h</Filter>

    </ClInclude>
@@ -621,7 +615,7 @@ 
      <Filter>common_h</Filter>

    </ClInclude>

    <ClInclude Include="..\lib_com\prot_fx.h">

      <Filter>common_all_c</Filter>

      <Filter>common_h</Filter>

    </ClInclude>

    <ClInclude Include="..\lib_com\complex_basop.h" />

    <ClInclude Include="..\lib_com\enh32.h" />

lib_com/bitstream.c

+0 −275
Original line number Diff line number Diff line
@@ -1660,281 +1660,6 @@ static void decoder_selectCodec( 
    return;

}



/*-------------------------------------------------------------------*

 * dec_prm_core()

 *

 *

 *-------------------------------------------------------------------*/



static void dec_prm_core(

    Decoder_State *st )

{

    int16_t n, frame_size_index = -1;



    st->core = -1;



    if ( st->total_brate == FRAME_NO_DATA )

    {

        st->m_frame_type = ZERO_FRAME;

    }

    else if ( st->total_brate == SID_2k40 )

    {

        st->m_frame_type = SID_FRAME;

    }

    else

    {

        st->m_frame_type = ACTIVE_FRAME;

        for ( n = 0; n < FRAME_SIZE_NB; ++n )

        {

            if ( FrameSizeConfig[n].frame_bits == st->total_brate / FRAMES_PER_SEC )

            {

                frame_size_index = n;

                break;

            }

        }



        /* Get audio bandwidth info */

        st->bwidth = get_next_indice( st, FrameSizeConfig[frame_size_index].bandwidth_bits );

        st->bwidth += FrameSizeConfig[frame_size_index].bandwidth_min;

        if ( st->bwidth > FB )

        {

            st->bwidth = FB;

            st->BER_detect = 1;

        }



        if ( st->bwidth > SWB && st->total_brate < ACELP_16k40 )

        {

            st->bwidth = SWB;

            st->BER_detect = 1;

        }

        /* Skip reserved bit */

        get_next_indice_tmp( st, FrameSizeConfig[frame_size_index].reserved_bits );



        if ( get_next_indice_1( st ) ) /* TCX */

        {

            if ( get_next_indice_1( st ) )

            {

                st->core = HQ_CORE;

            }

            else

            {

                st->core = TCX_20_CORE;

            }

        }

        else /* ACELP */

        {

            st->core = ACELP_CORE;

        }

    }



    return;

}



/*-----------------------------------------------------------------*

 * decision_matrix_core_dec()

 *

 * Read core signaling bits from the bitstream

 * Set st->core, and st->bwidth if signalled together with the core.

 *-----------------------------------------------------------------*/



static void decision_matrix_core_dec(

    Decoder_State *st /* i/o: decoder state structure                   */

)

{

    int16_t start_idx;

    int32_t ind;

    int16_t nBits;



    assert( st->bfi != 1 );



    st->core = -1;

    st->bwidth = -1;



    if ( st->total_brate == FRAME_NO_DATA || st->total_brate == SID_2k40 )

    {

        st->core = ACELP_CORE;

    }

    /* SC-VBR */

    else if ( st->total_brate == PPP_NELP_2k80 )

    {

        st->core = ACELP_CORE;

        return;

    }



    /*---------------------------------------------------------------------*

     * ACELP/HQ core selection

     *---------------------------------------------------------------------*/



    if ( st->total_brate < ACELP_24k40 )

    {

        st->core = ACELP_CORE;

    }

    else if ( st->total_brate >= ACELP_24k40 && st->total_brate <= ACELP_64k )

    {

        /* read the ACELP/HQ core selection bit */

        st->core = get_next_indice( st, 1 ) * HQ_CORE;

    }

    else

    {

        st->core = HQ_CORE;

    }



    /*-----------------------------------------------------------------*

     * Read ACELP signaling bits from the bitstream

     *-----------------------------------------------------------------*/



    if ( st->core == ACELP_CORE )

    {

        /* find the section in the ACELP signaling table corresponding to bitrate */

        start_idx = 0;

        while ( acelp_sig_tbl[start_idx] != st->total_brate )

        {

            start_idx++;

        }



        /* skip the bitrate */

        start_idx += 1;



        /* retrieve the number of bits */

        nBits = (int16_t) acelp_sig_tbl[start_idx++];



        /* retrieve the signaling indice */

        ind = acelp_sig_tbl[start_idx + get_next_indice( st, nBits )];

        st->bwidth = ( ind >> 3 ) & 0x7;



        /* convert signaling indice into signaling information */

        if ( ( ind & 0x7 ) == LR_MDCT )

        {

            st->core = HQ_CORE;

        }

    }



    /*-----------------------------------------------------------------*

     * Read HQ signaling bits from the bitstream

     * Set HQ core type

     *-----------------------------------------------------------------*/



    if ( st->core == HQ_CORE )

    {

        /* read the HQ/TCX core switching flag */

        if ( get_next_indice( st, 1 ) )

        {

            st->core = TCX_20_CORE;

        }



        /* For TCX: read/set band-width (needed for different I/O sampling rate support) */

        if ( st->core == TCX_20_CORE && st->total_brate > ACELP_16k40 )

        {

            ind = get_next_indice( st, 2 );



            if ( ind == 0 )

            {

                st->bwidth = NB;

            }

            else if ( ind == 1 )

            {

                st->bwidth = WB;

            }

            else if ( ind == 2 )

            {

                st->bwidth = SWB;

            }

            else

            {

                st->bwidth = FB;

            }

        }

    }



    return;

}



/*-------------------------------------------------------------------*

 * mdct_switching_dec()

 *

 * Set up MDCT core switching if indicated in the bitstream

 *-------------------------------------------------------------------*/



void mdct_switching_dec_ivas_fx(

    Decoder_State *st /* i/o: decoder state structure     */

)

{

    if ( !st->bfi )

    {



        if ( st->Opt_AMR_WB )

        {

            return;

        }





        if ( st->total_brate == ACELP_13k20 || st->total_brate == ACELP_32k )

        {

            st->mdct_sw_enable = MODE1;

        }

        else if ( ACELP_16k40 <= st->total_brate && st->total_brate <= ACELP_24k40 )

        {

            st->mdct_sw_enable = MODE2;

        }



        if ( st->codec_mode == MODE1 && st->mdct_sw_enable == MODE1 )

        {

            /* Read ahead core signaling */

            int16_t next_bit_pos_save = st->next_bit_pos;

            int16_t core_save = st->core;

            int16_t bwidth_save = st->bwidth;



            decision_matrix_core_dec( st ); /* sets st->core */



            if ( st->core == TCX_20_CORE )

            {

                /* Trigger TCX */

                st->codec_mode = MODE2;

                st->mdct_sw = MODE1;

            }

            else

            {

                /* Rewind bitstream */

                st->next_bit_pos = next_bit_pos_save;

                if ( st->bfi )

                {

                    st->core = core_save;

                    st->bwidth = bwidth_save;

                }

            }

        }

        else if ( st->codec_mode == MODE2 && st->mdct_sw_enable == MODE2 )

        {

            /* Read ahead core signaling */

            int16_t next_bit_pos_save = st->next_bit_pos;

            int16_t core_save = st->core;

            int16_t bwidth_save = st->bwidth;



            dec_prm_core( st ); /* sets st->core */



            if ( st->core == HQ_CORE )

            {

                /* Trigger HQ_CORE */

                st->codec_mode = MODE1;

                st->mdct_sw = MODE2;

            }

            else

            {

                /* Rewind bitstream */

                st->next_bit_pos = next_bit_pos_save;

                if ( st->bfi )

                {

                    st->core = core_save;

                }

                /* always reset bwidth, to not interfere with BER logic */

                st->bwidth = bwidth_save;

            }

        }

    }



    return;

}





/*-------------------------------------------------------------------*

 * reset_elements()

lib_com/bitstream_fx.c

+142 −959

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