There is probably a bug in the ACELP synthesis saved for SWB BWE in DTX (SID and NO_DATA frames) at https://forge.3gpp.org/rep/sa4/audio/ivas-basop/-/blob/main/lib_dec/acelp_core_dec_ivas_fx.c#L793. When comparing this code with EVS, a fix might be needed as follows: ``` /* save and delay synthesis to be used by SWB BWE */ Copy_Scale_sig( syn1_fx, temp_buf_fx, st->L_frame, sub( -1, st->Q_syn ) ); // Q_syn IF( st->hBWE_FD != NULL ) { #ifdef FIX save_old_syn_fx( st->L_frame, temp_buf_fx, old_syn_12k8_16k_fx, st->hBWE_FD->old_syn_12k8_16k_fx, st->preemph_fac, &st->hBWE_FD->mem_deemph_old_syn_fx ); #else save_old_syn_fx( st->L_frame, syn1_fx, old_syn_12k8_16k_fx, st->hBWE_FD->old_syn_12k8_16k_fx, st->preemph_fac, &st->hBWE_FD->mem_deemph_old_syn_fx ); #endif } ``` Please verify this instance.