Commit 0f9dcd33 authored by TYAGIRIS's avatar TYAGIRIS
Browse files

ref file name fixes

parent 7401270c

tests/test_sba_bs_dec_plc.py

+1 −1
Original line number Diff line number Diff line
@@ -143,7 +143,7 @@ def sba_dec_plc( 
    # ------------  run cmd  ------------



    tag_out = f"{tag}_ivasbr{ivas_br[:-3]}k_DTX{dtx}"

    if gain_flag != -1:

    if gain_flag == 1:

        tag_out += f'_Gain{gain_flag}'

    plc_tag_out = f"{tag_out}_{plc_pattern}"

tests/test_sba_bs_enc.py

+4 −4
Original line number Diff line number Diff line
@@ -487,7 +487,7 @@ def sba_enc( 
    if ivas_br == 'sw_24k4_256k.bin':

        ivas_br = f"{br_switch_file_path}/sw_24k4_256k.bin"   

    short_tag_ext = ""

    if gain_flag != -1:

    if gain_flag == 1:

        short_tag_ext += f'_Gain{gain_flag}'

    if SID == 1:

        short_tag_ext += f'_SID'
@@ -495,7 +495,7 @@ def sba_enc( 
    if bypass in [0, 2]:

        short_tag_ext += f"_pca{bypass}"

    # to avoid conflicting names in case of parallel test execution, differentiate all cases

    if gain_flag != -1:

    if gain_flag == 1:

        long_tag_ext = f"_Gain{gain_flag}"

    else:

        long_tag_ext = f"_pca{bypass}"
@@ -607,7 +607,7 @@ def sba_dec( 
    tag_out = f"{tag}_ivasbr{ivas_br[:-3]}k_DTX{dtx}"



    short_tag_ext = ""

    if gain_flag != -1:

    if gain_flag == 1:

        short_tag_ext += f'_Gain{gain_flag}'

    # we update only bypass = 0/2 (bypass 1 is the same as the baseline)

    if bypass in [0, 2]:
@@ -615,7 +615,7 @@ def sba_dec( 
    if SID == 1:

       short_tag_ext += f'_SID_cut'

    # to avoid conflicting names in case of parallel test execution, differentiate all cases

    if gain_flag != -1:

    if gain_flag == 1:

        long_tag_ext = f"_Gain{gain_flag}"

    else:

        long_tag_ext = f"_pca{bypass}"