Commit 29676d81 authored Jan 03, 2023 by premathasara

Change tests to to bit exactness

parent c2fd9dcb

tests/test_sba_bs_dec_plc.py

+1 −1

Original line number	Diff line number	Diff line
		@@ -49,7 +49,7 @@ ivas_br_list = ['32000', '64000', '96000', '256000']
		sampling_rate_list = ['48', '32', '16']
		agc_list = [-1, 0, 1]

		AbsTol = '3'
		AbsTol = '0'


		def check_and_makedir(dir_path):

tests/test_sba_bs_enc.py

+1 −1

Original line number	Diff line number	Diff line
		@@ -63,7 +63,7 @@ agc_list = [-1, 0, 1]

		sample_rate_bw_idx_list = [('48', 'SWB'), ('48', 'WB'), ('32', 'WB')]

		AbsTol = '4'
		AbsTol = '0'


		def check_and_makedir(dir_path):