cleanup of FDNCGVQ ROM OPT, builds on cygwin and msvc (4df74bf3) · Commits · IVAS Codec Public Collaboration / IVAS Codec

lib_com/cnst.h

+0 −4

Original line number	Diff line number	Diff line
		@@ -755,11 +755,7 @@ typedef enum
		#define STEP_SID 5.25f /* CNG & DTX - CNG energy quantization step */

		#define MIN_ACT_CNG_UPD 20 /* DTX - Minimum number of consecutive active frames for CNG mode update */
		#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING
		#define FIXED_SID_RATE 2 /* increase DTX SID rate for better FDCNG VQ testing */
		#else
		#define FIXED_SID_RATE 8 /* DTX SID rate */
		#endif

		#define TOTALNOISE_HIST_SIZE 4

lib_com/ivas_error_utils.h

+0 −3

Original line number	Diff line number	Diff line
		@@ -83,9 +83,6 @@ static inline ivas_error ivas_error_wrapper( const ivas_error error_code, const
		va_end( args );

		fprintf( stderr, "\n\nIn function: %s(), %s:%d\n\n", function, file, line );
		#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING
		assert( 0 );
		#endif
		// assert( 0 );

		return error_code;

lib_com/lsf_tools.c

+57 −140

Original line number	Diff line number	Diff line
		@@ -2031,7 +2031,7 @@ int16_t tcxlpc_get_cdk(
		void dec_FDCNG_MSVQ_stage1(
		int16_t j_full, /* i: index full range */
		int16_t n, /* i: dimension to generate */
		const float invTrfMatrix, / i: matrix for synthesis */
		const float invTrfMatrix, / i: IDCT matrix for synthesis */
		const DCTTYPE idcttype, /* i: specify which IDCT */
		float uq, / o: synthesized stage1 vector */
		Word16 uq_ind / o: synthesized stage1 vector in BASOP */
		@@ -2066,22 +2066,17 @@ void dec_FDCNG_MSVQ_stage1(

		for ( col = 0; col < cdk1_ivas_cols_per_segment[segm_ind]; col++ )
		{
		#if 1
		dct_vec[col] = (float) ( ( (Word16) cbpW8[col] ) << dct_col_shift_tab[col] );
		#else
		#define WMC_TOOL_MAN
		dct_vec[col] = (float) ( ( (Word16) cbpW8[col] ) << dct_col_shift_tab[col] );
		LOGIC( 1 );
		SHIFT( 1 );
		ADD( 1 ); /* in BASOP: s_and(for W8->W16), shl(), sub()*/
		#undef WMC_TOOL_MAN
		#endif
		/* LOGIC( 1 );SHIFT( 1 ); ADD( 1 );
		in BASOP: s_and(for W8->W16), shl(), sub()
		*/
		}
		dctT2_N_apply_matrix( (const float *) dct_vec, idct_vec, cdk1_ivas_cols_per_segment[segm_ind], n, invTrfMatrix, FDCNG_VQ_DCT_MAXTRUNC, idcttype );

		/scale down to original fdcngvq domain and move to Q0 /
		v_multc( idct_vec, fdcng_dct_scaleF[1], idct_vec, n );
		/* fdcng_dct_scaleF[1] --> 0.0625-->scale down from search Q4 domain to Q0 , not really relevant for BASOP loop */
		/* fdcng_dct_scaleF[1] --> 0.0625-->scale down from search Q4 domain to Q0 ,
		not really relevant for BASOP loop */

		/add common mid fdcng vector, in fdcng bands domain /
		v_add( idct_vec, cdk1r_tr_midQ_truncQ, uq, n );
		@@ -2107,7 +2102,7 @@ void msvq_dec(
		const int16_t Idx[], /* i : Indices */
		#ifdef ERI_FDCNGVQ_LOW_ROM
		const int16_t applyIDCT_flag, /* i : applyIDCT flag */
		const float invTrfMatrix, / i: matrix for synthesis */
		const float invTrfMatrix, / i: matrix for IDCT synthesis */
		#endif
		float uq, / o : quantized vector */
		Word16 uq_ind / o : quantized vector (fixed point) */
		@@ -2150,7 +2145,7 @@ void msvq_dec(
		if ( i == 0 && applyIDCT_flag != 0 )
		{
		assert( start == 0 );
		dec_FDCNG_MSVQ_stage1( Idx[0], N, invTrfMatrix, IDCT_T2_XX_24, uq, uq_ind ); /* IDCT24 used for all synthesis */
		dec_FDCNG_MSVQ_stage1( Idx[0], N, invTrfMatrix, IDCT_T2_XX_24, uq, uq_ind ); /* IDCT_T2 N=24 used for all synthesis */
		}
		else
		{
		@@ -2454,7 +2449,7 @@ void a2isf(
		/-------------------------------------------------------------------
		* dctT2_N_apply_matrix()
		*
		* dct/idct matrix application loop for a fixed DCT basis vector length of N
		* dct/idct truncated matrix appl. for DCT basis vector lengths of N
		-------------------------------------------------------------------/
		void dctT2_N_apply_matrix(
		const float *input,
		@@ -2471,17 +2466,9 @@ void dctT2_N_apply_matrix(
		float tmp_y[FDCNG_VQ_MAX_LEN];
		float *pt_y;

		#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING
		{
		char tmp_str[1024];
		sprintf( tmp_str, "dctT2_%d_apply_mat", fdcngvq_dim );
		push_wmops( tmp_str );
		}
		#endif

		/* [optionally] non-square DCT_N and IDCT_N matrix application,
		/* non-square DCT_N and IDCT_N matrix application,
		using a stored format of an IDCT_Nx(FDCNG_VQ_DCT_MAXTRUNC) matrix */
		/* effciently parallelized in SIMD */
		/* efficiently parallelized in SIMD */

		assert( dct_dim <= FDCNG_VQ_DCT_MAXTRUNC );
		assert( fdcngvq_dim <= FDCNG_VQ_MAX_LEN );
		@@ -2511,7 +2498,6 @@ void dctT2_N_apply_matrix(
		for ( i = 0; i < dim_out; i++ )
		{
		pt_x = input;

		*pt_y = 0;

		/* +i(DCT) or +imaxTrunc(IDCT) /
		@@ -2523,20 +2509,14 @@ void dctT2_N_apply_matrix(
		{
		#define WMC_TOOL_SKIP
		pt_y += ( pt_x++ ) * ( *pt_A );
		pt_A += mat_step_col; /* step +maxtrunc or 1 / / ptr indexing*/
		pt_A += mat_step_col; /* step +maxtrunc or +1 / / ptr indexing*/
		MAC( 1 );
		#undef WMC_TOOL_SKIP
		}
		pt_y++;
		}
		mvr2r( tmp_y, output, dim_out );
		#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING
		{
		pop_wmops();
		}
		#endif
		}


		/-------------------------------------------------------------------
		* extend_dctN_input()
		@@ -2551,41 +2531,28 @@ void extend_dctN_input(
		const int16_t in_dim, /* i: in_dim == N */
		float ext_sig, / o: extended output in fdcng domain */
		const int16_t out_dim, /* i: output total dim */
		float matrix, / i: idct synthesis matrix of size N rows , n_cols columns*/
		const int16_t n_cols, /* i: number of columns == truncation length */
		float matrix, / i: idct synthesis matrix N rows, n_cols columns */
		const int16_t n_cols, /* i: number of columns == DCT truncation length */
		DCTTYPE dcttype ) /* i: matrix operation type */
		{
		int16_t i, j, i_rev;

		const float( ptr )[FDCNG_VQ_DCT_MAXTRUNC] = (void ) matrix;

		#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING
		{
		char tmp_str[1024];
		sprintf( tmp_str, "extend_dct%d_input", in_dim );
		push_wmops( tmp_str );
		}
		#endif


		/* stored format of an IDCT_Nx(FDCNG_VQ_DCT_MAXTRUNC) matrix */
		/* stored format is an IDCT_Nx(FDCNG_VQ_DCT_MAXTRUNC) matrix */
		assert( in_dim < FDCNG_VQ_MAX_LEN );
		assert( out_dim <= FDCNG_VQ_MAX_LEN );
		assert( out_dim > in_dim );
		assert( n_cols == FDCNG_VQ_DCT_MAXTRUNC ); /* for ptr[MAX_TRUNC] adressing/
		assert( ( dcttype & 1 ) != 0 ); /* idct tables always in use for this basis vector extension */


		assert( ( dcttype & 1 ) != 0 ); /* idct tables in use for this basis vector extension */

		mvr2r( input, ext_sig, in_dim ); /* copy initial part, i.e. only last/tail parts are updated */

		mvr2r( input, ext_sig, in_dim ); /* copy initial part, i.e. only last/tail parts are extended */
		set_f( &( ext_sig[in_dim] ), 0.0, out_dim - in_dim );

		i_rev = in_dim; /ptr init/
		for ( i = in_dim; i < out_dim; i++ )
		{ /* for each extension sample */
		/* i = 21 22 23;
		i_rev = 20 19 18; for odd dctII simply reflect basis vector
		i_rev = 20 19 18; for odd dctII reflect basis vector
		*/
		i_rev--;

		@@ -2593,53 +2560,41 @@ void extend_dctN_input(
		{
		/* DCTcoeff * reflected basis vector */
		#define WMC_TOOL_SKIP
		/* these are pure ptr operations */
		/* pure ptr MAC operations */
		ext_sig[i] += dct_input[j] * ptr[i_rev][j]; /* sum up scaled and extended basis vector */
		MAC( 1 );
		#undef WMC_TOOL_SKIP
		}
		}
		#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING
		{
		pop_wmops();
		}
		#endif
		}


		/* inititate idct24 FDCNG_VQ_DCT_MAXTRUNCx N matrix in RAM from a Word8+Word16 quantized compressed ROM format */
		/* inititate idct24 FDCNG_VQ_DCT_MAXTRUNCx N matrix in RAM from a quantized compressed ROM format */
		void create_IDCT_N_Matrix( float *inv_matrixFloatQ, const int16_t N, const int16_t n_cols, const int16_t alloc_size )
		{
		int16_t c, c1, r, r_flip, W16_val;
		int16_t len; /* <=FDCNG_VQ_MAX_LEN */
		int16_t len;
		int16_t mat_cpy_size;
		const Word16 *val_ptr;
		const Word16 *absval_ptr;
		const Word8 *idx_ptr;
		int8_t idx;
		#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING
		{
		char tmp_str[1024];
		sprintf( tmp_str, "create_IDCT_%d_mat", N );
		push_wmops( tmp_str );
		}
		#endif
		Word16 idx;
		float( ptr )[FDCNG_VQ_DCT_MAXTRUNC] = (void ) inv_matrixFloatQ; /* fixed number of columns pointers, to simplifies adressing in ANSIC */


		val_ptr = unique_idctT2_24coeffsQ16;
		absval_ptr = unique_idctT2_24coeffsQ16;
		idx_ptr = idctT2_24_compressed_idx;
		len = FDCNG_VQ_MAX_LEN;

		if ( N == FDCNG_VQ_MAX_LEN_WB )
		{
		val_ptr = unique_idctT2_21coeffsQ16;
		absval_ptr = unique_idctT2_21coeffsQ16;
		idx_ptr = idctT2_21_compressed_idx;
		len = N;
		}

		assert( alloc_size >= ( n_cols * len ) ); /* enough space for the full expanded IDCT matrix */
		assert( N <= len );
		W16_val = 0; /* safety init */

		mat_cpy_size = ( n_cols ) * ( len / 2 ); /* one integer division of "len" */
		mat_cpy_size = ( n_cols ) * ( len >> 1 ); /* NB integer division of "len" */

		if ( ( len & 1 ) != 0 )
		{ /* odd sized DCT with a non-reflected center row */
		@@ -2648,32 +2603,23 @@ void create_IDCT_N_Matrix( float *inv_matrixFloatQ, const int16_t N, const int16

		for ( c = 0; c < mat_cpy_size; c++ )
		{
		idx = idx_ptr[c];
		if ( idx >= 0 )
		{
		W16_val = ( val_ptr[idx] );
		}
		idx = (Word16) ( idx_ptr[c] );
		W16_val = absval_ptr[abs( idx )];

		if ( idx < 0 )
		{
		W16_val = -( val_ptr[-idx] );
		W16_val = -( W16_val );
		}
		inv_matrixFloatQ[c] = ( +1.52587890625e-05f ) * ( (float) W16_val ); /* 1.0/2.^16 scaling to a float-"Q0" scaling not done in BASOP */
		inv_matrixFloatQ[c] = ( +1.52587890625e-05f ) * ( (float) W16_val ); /* 1.0/2.^16 scaling to a float-"Q0" , a scaling that is not done in BASOP */
		}

		{ /* a temporary local scope for matrix ptr's */
		/* for even number of coeffs DCT24,
		flip symmetry for odd, even used to save 50% further Table ROM */
		/* for odd DCT center is not flipped e.g DCT21 */
		/* float inv_matrixFloatQ[len][FDCNG_VQ_DCT_MAXTRUNC]; */

		/* use fixed number of columns pointers , to simplify adressing code below */
		float( ptr )[FDCNG_VQ_DCT_MAXTRUNC] = (void ) inv_matrixFloatQ;
		float( ptr21 )[FDCNG_VQ_MAX_LEN_WB] = (void ) inv_matrixFloatQ;

		if ( n_cols == FDCNG_VQ_DCT_MAXTRUNC )
		{
		flip symmetry for odd, even is used to save 50% IDCT Table ROM */
		/* for an odd DCT center is not flipped e.g for DCT21 */

		assert( n_cols == FDCNG_VQ_DCT_MAXTRUNC );
		assert( ( n_cols & 1 ) == 0 );

		for ( c = 0; c < ( n_cols ); c += 2 )
		{
		c1 = c + 1;
		@@ -2681,43 +2627,14 @@ void create_IDCT_N_Matrix( float *inv_matrixFloatQ, const int16_t N, const int16
		for ( r = 0; r < ( len / 2 ); r++, r_flip-- )
		{
		#define WMC_TOOL_SKIP
		/* pure ptr based calculations */
		ptr[r_flip][c] = ptr[r][c]; /* flipped */
		ptr[r_flip][c1] = -ptr[r][c1]; /* flipped and sign swapped */

		ptr[r_flip][c1] = -( ptr[r][c1] ); /* flipped and sign swapped */
		MOVE( 2 );
		MULT( 1 ); /* for negate */
		#undef WMC_TOOL_SKIP
		}
		}
		}
		else
		{
		float sign_swap = 1.0f;
		assert( n_cols == FDCNG_VQ_MAX_LEN_WB );
		for ( c = 0; c < ( n_cols ); c++ )
		{
		r_flip = len - 1;
		sign_swap = 1.0f - 2.0f * ( c & 1 ); /signsawpp odd columns /
		for ( r = 0; r < ( len / 2 ); r++, r_flip-- )
		{
		#define WMC_TOOL_SKIP
		/* pure ptr based calculations */
		ptr21[r_flip][c] = sign_swap * ptr21[r][c]; /* flipped and potetially sign swapped */

		MULT( 1 );
		MOVE( 1 );
		#undef WMC_TOOL_SKIP
		}
		}
		}
		}
		#ifdef ERI_FDCNGVQ_LOW_ROM_TESTING
		{
		pop_wmops();
		}
		#endif
		}


		#endif

lib_com/options.h

+2 −3

Original line number	Diff line number	Diff line
		@@ -83,7 +83,7 @@
		/#define ALLOW_BYTE_EP/ /* allow byte fer pattern files and check fer pattern file validity */
		#define WRAP_AS_EIDXOR /* wraps FER file (as in STL_eid-xor.c/softbit.c) */

		#define DEBUG_FORCE_MDCT_STEREO_MODE /* Force stereo mode decision for MDCT stereo: -stere 3 1 forces L/R coding and -stereo 3 2 forces full M/S coding */
		#define DEBUG_FORCE_MDCT_STEREO_MODE /* Force stereo mode decision for MDCT stereo: -stereo 3 1 forces L/R coding and -stereo 3 2 forces full M/S coding */
		/#define DEBUG_STEREO_DFT_NOCORE/ /* DFT stereo: by-pass core coder at decoder side*/
		/#define DEBUG_STEREO_DFT_NOSTEREO/ /* DFT stereo: by-pass stereo processing at encoder and decoder side*/
		/#define DEBUG_STEREO_DFT_NOQRES/
		@@ -174,8 +174,7 @@



		#define ERI_FDCNGVQ_LOW_ROM /* Eri: ~1.6kW Table ROM saving for IVAS FDCNG-VQ */
		/# define ERI_FDCNGVQ_LOW_ROM_TESTING / /* Enable testing vs. Baseline for XC SD-measurements , deactivate for WMOPS measurement */
		#define ERI_FDCNGVQ_LOW_ROM /* Eri: Contribution #31 Table ROM saving for IVAS FDCNG-VQ modes */

		/* ################## End DEVELOPMENT switches ######################### */
		/* clang-format on */

lib_com/prot.h

+15 −17

Original line number	Diff line number	Diff line
		@@ -8103,24 +8103,22 @@ void dec_FDCNG_MSVQ_stage1(
		Word16 uq_ind / o: synthesized stage1 vector in BASOP */
		);


		void create_IDCT_N_Matrix(
		float inv_matrixFloatQ, / i/o: RAM buffer */
		const int16_t N, /* i: DCT length , number of time samples */
		const int16_t n_cols, /i: number of dct coeffs (as DCt may be truncated /

		const int16_t n_cols, /* i: number of dct coeffs (as DCT may be truncated) */
		const int16_t alloc_size /* i: RAM buffer size in elements*/
		);


		void dctT2_N_apply_matrix(
		const float *input,
		float *output,
		const int16_t dct_dim,
		int16_t fdcngvq_dim,
		const float *idctT2_N_16matrixQ16,
		const int16_t matrix_1st_dim,
		DCTTYPE dcttype );
		const float input, / i: input in fdcng or DCT(fdcng) domain */
		float output, / o: output in DCT(fdcng) or fdcng ordomain */
		const int16_t dct_dim, /* i: dct processing dim possibly truncated */
		int16_t fdcngvq_dim, /* i: fdcng domain length */
		const float idctT2_N_16matrixQ16, / i: IDCT matrix */
		const int16_t matrix_1st_dim, /* i: */
		DCTTYPE dcttype ); /* i: matrix operation type */

		void extend_dctN_input(
		const float input, / i: input in fdcng domain */
		@@ -8130,7 +8128,7 @@ void extend_dctN_input(
		const int16_t out_dim, /* i: output total dim */
		float matrix, / i: idct matrix of size N rows , n_cols columns*/
		const int16_t n_cols, /* i: number of columns == truncation length */
		DCTTYPE dcttype ); /* i: matrix operation type */
		DCTTYPE dcttype ); /* i: matrix type */
		#endif

		void PulseResynchronization(