Loading lib_com/options.h +1 −0 Original line number Diff line number Diff line Loading @@ -177,6 +177,7 @@ #define NONBE_1220_OMASA_JBM_BRATE_SW_FLUSH /* VA: issue 1220: fix bug in renderer flush in OMASA 1ISM JBM bitrate switching */ #define NONBE_1229_FIX_ISM1_DPID /* Eri: issue 1229: fix bug causing ISM 1 to use default -dpid instead of the specified one */ #define NONBE_1233_HQ_CLASSIFIER_DIV_BY_ZERO /* Eri: issue 1233: Address possible division by zero in hf_spectrum_sparseness() */ #define NONBE_1214_PLC_LSF_MEMORY /* VA: issue 1224: reset ACELP PLC FEC memory in case of switching from MDCT stereo to TD/DFT stereo */ /* ##################### End NON-BE switches ########################### */ Loading lib_dec/core_switching_dec.c +6 −0 Original line number Diff line number Diff line Loading @@ -263,8 +263,14 @@ ivas_error core_switching_pre_dec( st->uv_count = 0; } #ifdef NONBE_1214_PLC_LSF_MEMORY if ( ( ( st->core == ACELP_CORE || st->core == AMR_WB_CORE ) && ( st->last_core == HQ_CORE || last_element_mode == IVAS_CPE_MDCT ) ) || ( ( st->element_mode == IVAS_CPE_DFT || st->element_mode == IVAS_CPE_TD || ( st->element_mode == IVAS_CPE_MDCT && last_element_mode == IVAS_CPE_DFT ) ) && nchan_out == 2 && st->core_brate != SID_2k40 && st->core_brate != FRAME_NO_DATA && ( last_core_brate_st0 == FRAME_NO_DATA || last_core_brate_st0 == SID_2k40 ) ) ) #else if ( ( ( st->core == ACELP_CORE || st->core == AMR_WB_CORE ) && st->last_core == HQ_CORE ) || ( ( st->element_mode == IVAS_CPE_DFT || st->element_mode == IVAS_CPE_TD || ( st->element_mode == IVAS_CPE_MDCT && last_element_mode == IVAS_CPE_DFT ) ) && nchan_out == 2 && st->core_brate != SID_2k40 && st->core_brate != FRAME_NO_DATA && ( last_core_brate_st0 == FRAME_NO_DATA || last_core_brate_st0 == SID_2k40 ) ) ) #endif { if ( st->element_mode == IVAS_CPE_DFT || st->element_mode == IVAS_CPE_TD ) { Loading Loading
lib_com/options.h +1 −0 Original line number Diff line number Diff line Loading @@ -177,6 +177,7 @@ #define NONBE_1220_OMASA_JBM_BRATE_SW_FLUSH /* VA: issue 1220: fix bug in renderer flush in OMASA 1ISM JBM bitrate switching */ #define NONBE_1229_FIX_ISM1_DPID /* Eri: issue 1229: fix bug causing ISM 1 to use default -dpid instead of the specified one */ #define NONBE_1233_HQ_CLASSIFIER_DIV_BY_ZERO /* Eri: issue 1233: Address possible division by zero in hf_spectrum_sparseness() */ #define NONBE_1214_PLC_LSF_MEMORY /* VA: issue 1224: reset ACELP PLC FEC memory in case of switching from MDCT stereo to TD/DFT stereo */ /* ##################### End NON-BE switches ########################### */ Loading
lib_dec/core_switching_dec.c +6 −0 Original line number Diff line number Diff line Loading @@ -263,8 +263,14 @@ ivas_error core_switching_pre_dec( st->uv_count = 0; } #ifdef NONBE_1214_PLC_LSF_MEMORY if ( ( ( st->core == ACELP_CORE || st->core == AMR_WB_CORE ) && ( st->last_core == HQ_CORE || last_element_mode == IVAS_CPE_MDCT ) ) || ( ( st->element_mode == IVAS_CPE_DFT || st->element_mode == IVAS_CPE_TD || ( st->element_mode == IVAS_CPE_MDCT && last_element_mode == IVAS_CPE_DFT ) ) && nchan_out == 2 && st->core_brate != SID_2k40 && st->core_brate != FRAME_NO_DATA && ( last_core_brate_st0 == FRAME_NO_DATA || last_core_brate_st0 == SID_2k40 ) ) ) #else if ( ( ( st->core == ACELP_CORE || st->core == AMR_WB_CORE ) && st->last_core == HQ_CORE ) || ( ( st->element_mode == IVAS_CPE_DFT || st->element_mode == IVAS_CPE_TD || ( st->element_mode == IVAS_CPE_MDCT && last_element_mode == IVAS_CPE_DFT ) ) && nchan_out == 2 && st->core_brate != SID_2k40 && st->core_brate != FRAME_NO_DATA && ( last_core_brate_st0 == FRAME_NO_DATA || last_core_brate_st0 == SID_2k40 ) ) ) #endif { if ( st->element_mode == IVAS_CPE_DFT || st->element_mode == IVAS_CPE_TD ) { Loading