Commit b1f78744 authored by norvell's avatar norvell
Browse files

Merge with main

parents 898f904c 9f0ec81c
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+1 −1
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@@ -2044,7 +2044,7 @@ coverage-test-on-main-scheduled:
    - python3 -m pytest $TESTS_DIR_CODEC_BE_ON_MR -v -n auto --update_ref 1 -m create_ref_part2 --ref_encoder_path ./IVAS_cod --ref_decoder_path ./IVAS_dec
    # need to ignore non-zero exit codes as limiter is active and thus the different framesiszes will not be BE in all cases
    - python3 -m pytest $TESTS_DIR_CODEC_BE_ON_MR -v --dut_encoder_path ./IVAS_cod --dut_decoder_path ./IVAS_dec --dut_fr 5 --decoder_only || true
    - python3 -m pytest $TESTS_DIR_CODEC_BE_ON_MR -v --dut_encoder_path ./IVAS_cod --dut_decoder_path ./IVAS_dec --dut_fr 10 --decoder_only || true
    - python3 -m pytest $TESTS_DIR_CODEC_BE_ON_MR -v --dut_encoder_path ./IVAS_cod --dut_decoder_path ./IVAS_dec --dut_fr 10 --decoder_only || true
    - python3 -m pytest -q -n auto tests/renderer/test_renderer.py --create_ref
    - python3 -m pytest -q -n auto tests/renderer/test_renderer.py --create_cut    
    - lcov -c -d obj -o coverage_stv.info # extract coverage of short test vectors here
+2 −2
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@@ -156,11 +156,11 @@
/*#define FIX_I4_OL_PITCH*/                             /* fix open-loop pitch used for EVS core switching */
/*#define SPLIT_REND_WITH_HEAD_ROT  */                  /* Dlb,FhG: Split Rendering contributions 21 and 35 */


#define FIX_998_UNUSED_FUNCTION                         /* FhG: issue 998: delete unused funtion ivas_dirac_dec_get_response_split_order */ 
#define FIX_1009_ISM_NONDIEGETIC_PANNING                /* FhG: issue #1009: use correct object buffer for ISM1 non-diegetic pan      */
#define FIX_993_REMOVE_SBA_GET_ORDER                    /* VA: issue 993: remove unused function ivas_sba_get_order() */
#define FIX_1002_DEC_PHASE_ECU_USAN_OF_PHASE            /* Eri: issue #1002, usan-value-out-of-range-for-int16, kept BE for PLC-conditions   */
#define FIX_960_SYN_OUTPUT                              /* VA: issue 960: unused function syn_output() is removed */

/* #################### End BE switches ################################## */

+4 −0
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@@ -161,12 +161,14 @@ int16_t sum_s(
    const int16_t lvec  /* i  : length of input vector                          */
);

#ifdef DEBUGGING
/*! r: sum of all vector elements */
int32_t sum_l(
    const int32_t *vec, /* i  : input vector                                    */
    const int16_t lvec  /* i  : length of input vector                          */
);

#endif
/*! r: sum of all vector elements */
float sum_f(
    const float *vec,  /* i  : input vector                                    */
@@ -4822,12 +4824,14 @@ void dec_acelp_4t64(
    const int16_t Opt_AMR_WB /* i  : flag indicating AMR-WB IO mode                  */
);

#ifndef FIX_960_SYN_OUTPUT
uint32_t syn_output(
    float *synth,               /* i/o: float synthesis signal                          */
    const int16_t output_frame, /* i  : output frame length                             */
    int16_t *synth_out          /* o  : integer 16 bits synthesis signal                */
);

#endif
void FEC_exc_estim(
    Decoder_State *st,     /* i/o: Decoder static memory                           */
    const int16_t L_frame, /* i  : length of the frame                             */
+2 −0
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@@ -138,6 +138,7 @@ int16_t sum_s(
    return tmp;
}

#ifdef DEBUGGING
/*! r: sum of all vector elements */
int32_t sum_l(
    const int32_t *vec, /* i  : input vector                          */
@@ -156,6 +157,7 @@ int32_t sum_l(
    return tmpL;
}

#endif
/*! r: sum of all vector elements */
float sum_f(
    const float *vec,  /* i  : input vector                          */
+5 −0
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@@ -44,6 +44,10 @@
#include "prot.h"
#include "wmc_auto.h"


#ifdef FIX_960_SYN_OUTPUT
/* Note: syn_output() is replaced by ivas_syn_output() in IVAS */
#else
/*-------------------------------------------------------------------*
 * syn_output()
 *
@@ -65,6 +69,7 @@ uint32_t syn_output(
    /* integer conversion */
    return mvr2s( synth, synth_out, output_frame );
}
#endif


/*-------------------------------------------------------------------*
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