Loading lib_debug/flp_debug.h +4 −4 Original line number Diff line number Diff line Loading @@ -67,8 +67,8 @@ static inline void enable_denorm_trap(void) { __asm__ volatile("mrs %0, fpcr" : "=r"(fpcr)); // disable sits 24(FZ) & 25(DN) --> allow denormals to happen fpcr &= ~((1ull<<24)|(1ull<<25)); // set bit 3 (UFE) to unmask underflow exceptions fpcr |= (1ull<<3); // set bit 11 (UFE) to unmask underflow exceptions fpcr |= (1ull<<11); __asm__ volatile("msr fpcr, %0" :: "r"(fpcr)); #else Loading @@ -91,8 +91,8 @@ static inline void disable_denorm_trap(void) { // AArch64 (Apple Silicon) uint64_t fpcr; __asm__ volatile("mrs %0, fpcr" : "=r"(fpcr)); // delete bit 3 (UFE), set bits 24/25 (FZ/DN) again fpcr &= ~(1ull<<3); // delete bit 11 (UFE), set bits 24/25 (FZ/DN) again fpcr &= ~(1ull<<11); fpcr |= (1ull<<24)|(1ull<<25); __asm__ volatile("msr fpcr, %0" :: "r"(fpcr)); Loading Loading
lib_debug/flp_debug.h +4 −4 Original line number Diff line number Diff line Loading @@ -67,8 +67,8 @@ static inline void enable_denorm_trap(void) { __asm__ volatile("mrs %0, fpcr" : "=r"(fpcr)); // disable sits 24(FZ) & 25(DN) --> allow denormals to happen fpcr &= ~((1ull<<24)|(1ull<<25)); // set bit 3 (UFE) to unmask underflow exceptions fpcr |= (1ull<<3); // set bit 11 (UFE) to unmask underflow exceptions fpcr |= (1ull<<11); __asm__ volatile("msr fpcr, %0" :: "r"(fpcr)); #else Loading @@ -91,8 +91,8 @@ static inline void disable_denorm_trap(void) { // AArch64 (Apple Silicon) uint64_t fpcr; __asm__ volatile("mrs %0, fpcr" : "=r"(fpcr)); // delete bit 3 (UFE), set bits 24/25 (FZ/DN) again fpcr &= ~(1ull<<3); // delete bit 11 (UFE), set bits 24/25 (FZ/DN) again fpcr &= ~(1ull<<11); fpcr |= (1ull<<24)|(1ull<<25); __asm__ volatile("msr fpcr, %0" :: "r"(fpcr)); Loading