Commit d18c5af5 authored by vaclav's avatar vaclav
Browse files

#CR_FIX_735_SBA_HP20_BRATE_SWITCHING

parent 17a3401a
Loading
Loading
Loading
Loading
Loading
+2 −0
Original line number Diff line number Diff line
@@ -180,6 +180,8 @@
#define CR_FIX_586_BPF_DFT_MEM                          /* FhG: issue 586: set input memory of DFT analysis of BPF signal to zero for HQ core to fix issue with PLC and bitrate switching */
#define CR_FIX_ISM_DTX_INFINITE_CNG_ON_TRAILING_SILENCE /* FhG: fix for cng in ISM DTX on sudden silence periods */
#define CR_FIX_698_SBA_MSAN                             /* Dlb: issue 698: Uninitialized memory read in SBA init */
#define CR_FIX_735_SBA_HP20_BRATE_SWITCHING             /* VA: Resolve "HP20 filtering bug in SBA/OSBA bitrate switching" */


/* ##################### End NON-BE CR switches ########################### */

+12 −1
Original line number Diff line number Diff line
@@ -127,6 +127,16 @@ ivas_error ivas_enc(
    dbgwrite( data_f[LFE_CHANNEL], sizeof( float ), n_samples_chan, 1, "./res/lfe_input" );
#endif

#ifdef CR_FIX_735_SBA_HP20_BRATE_SWITCHING
    if ( ivas_format == SBA_FORMAT )
    {
        if ( ( error = ivas_sba_enc_reconfigure( st_ivas ) ) != IVAS_ERR_OK )
        {
            return error;
        }
    }
#endif

    /*----------------------------------------------------------------*
     * HP filtering
     *----------------------------------------------------------------*/
@@ -203,11 +213,12 @@ ivas_error ivas_enc(
        /* SBA/MASA configuration */
        if ( ivas_format == SBA_FORMAT )
        {
#ifndef CR_FIX_735_SBA_HP20_BRATE_SWITCHING
            if ( ( error = ivas_sba_enc_reconfigure( st_ivas ) ) != IVAS_ERR_OK )
            {
                return error;
            }

#endif
            st = ( st_ivas->nSCE > 0 ) ? st_ivas->hSCE[0]->hCoreCoder[0] : st_ivas->hCPE[0]->hCoreCoder[0];

            /* Write SBA planar flag */