Loading lib_com/bitstream.c +2 −4 Original line number Diff line number Diff line Loading @@ -1662,8 +1662,7 @@ static ivas_error write_indices_element( reset_indices_enc( st_ivas->hSCE[element_id]->hMetaData, st_ivas->hSCE[element_id]->hMetaData->nb_ind_tot ); } reset_indices_enc( sts[0]->hBstr, sts[0]->hBstr->nb_ind_tot ); reset_indices_enc( sts[0]->hBstr, sts[0]->hBstr->nb_ind_tot ); } else { Loading @@ -1674,8 +1673,7 @@ static ivas_error write_indices_element( for ( n = 0; n < n_channels; n++ ) { reset_indices_enc( sts[n]->hBstr, sts[n]->hBstr->nb_ind_tot ); reset_indices_enc( sts[n]->hBstr, sts[n]->hBstr->nb_ind_tot ); } } Loading lib_dec/ivas_corecoder_dec_reconfig.c +1 −0 Original line number Diff line number Diff line Loading @@ -237,6 +237,7 @@ ivas_error ivas_corecoder_dec_reconfig( { st_ivas->element_mode_init = IVAS_CPE_MDCT; } if ( ( error = create_cpe_dec( st_ivas, cpe_id, brate_CPE ) ) != IVAS_ERR_OK ) { return error; Loading lib_enc/dtx.c +1 −2 Original line number Diff line number Diff line Loading @@ -255,8 +255,7 @@ void dtx( /* reset the bitstream (IVAS format signaling was already written) */ if ( st->element_mode != IVAS_CPE_MDCT && st->hBstr != NULL ) { reset_indices_enc( st->hBstr, st->hBstr->nb_ind_tot ); reset_indices_enc( st->hBstr, st->hBstr->nb_ind_tot ); } } Loading lib_enc/enc_ppp.c +1 −3 Original line number Diff line number Diff line Loading @@ -169,9 +169,7 @@ ivas_error encod_ppp( } /* delete previous indices */ reset_indices_enc( hBstr, hBstr->nb_ind_tot ); reset_indices_enc( hBstr, hBstr->nb_ind_tot ); /* signaling matrix (writing of signaling bits) */ signaling_enc( st ); Loading lib_enc/fd_cng_enc.c +2 −4 Original line number Diff line number Diff line Loading @@ -923,11 +923,9 @@ void stereoFdCngCoherence( else if ( sts[0]->core_brate <= SID_2k40 && sts[1]->core_brate <= SID_2k40 ) { /* case: no VAD for both channels -> INACTIVE FRAME */ reset_indices_enc( sts[0]->hBstr, sts[0]->hBstr->nb_ind_tot ); reset_indices_enc( sts[0]->hBstr, sts[0]->hBstr->nb_ind_tot ); reset_indices_enc( sts[1]->hBstr, sts[1]->hBstr->nb_ind_tot ); reset_indices_enc( sts[1]->hBstr, sts[1]->hBstr->nb_ind_tot ); /* synchronize SID sending for variable SID rate */ if ( sts[0]->core_brate != sts[1]->core_brate ) Loading Loading
lib_com/bitstream.c +2 −4 Original line number Diff line number Diff line Loading @@ -1662,8 +1662,7 @@ static ivas_error write_indices_element( reset_indices_enc( st_ivas->hSCE[element_id]->hMetaData, st_ivas->hSCE[element_id]->hMetaData->nb_ind_tot ); } reset_indices_enc( sts[0]->hBstr, sts[0]->hBstr->nb_ind_tot ); reset_indices_enc( sts[0]->hBstr, sts[0]->hBstr->nb_ind_tot ); } else { Loading @@ -1674,8 +1673,7 @@ static ivas_error write_indices_element( for ( n = 0; n < n_channels; n++ ) { reset_indices_enc( sts[n]->hBstr, sts[n]->hBstr->nb_ind_tot ); reset_indices_enc( sts[n]->hBstr, sts[n]->hBstr->nb_ind_tot ); } } Loading
lib_dec/ivas_corecoder_dec_reconfig.c +1 −0 Original line number Diff line number Diff line Loading @@ -237,6 +237,7 @@ ivas_error ivas_corecoder_dec_reconfig( { st_ivas->element_mode_init = IVAS_CPE_MDCT; } if ( ( error = create_cpe_dec( st_ivas, cpe_id, brate_CPE ) ) != IVAS_ERR_OK ) { return error; Loading
lib_enc/dtx.c +1 −2 Original line number Diff line number Diff line Loading @@ -255,8 +255,7 @@ void dtx( /* reset the bitstream (IVAS format signaling was already written) */ if ( st->element_mode != IVAS_CPE_MDCT && st->hBstr != NULL ) { reset_indices_enc( st->hBstr, st->hBstr->nb_ind_tot ); reset_indices_enc( st->hBstr, st->hBstr->nb_ind_tot ); } } Loading
lib_enc/enc_ppp.c +1 −3 Original line number Diff line number Diff line Loading @@ -169,9 +169,7 @@ ivas_error encod_ppp( } /* delete previous indices */ reset_indices_enc( hBstr, hBstr->nb_ind_tot ); reset_indices_enc( hBstr, hBstr->nb_ind_tot ); /* signaling matrix (writing of signaling bits) */ signaling_enc( st ); Loading
lib_enc/fd_cng_enc.c +2 −4 Original line number Diff line number Diff line Loading @@ -923,11 +923,9 @@ void stereoFdCngCoherence( else if ( sts[0]->core_brate <= SID_2k40 && sts[1]->core_brate <= SID_2k40 ) { /* case: no VAD for both channels -> INACTIVE FRAME */ reset_indices_enc( sts[0]->hBstr, sts[0]->hBstr->nb_ind_tot ); reset_indices_enc( sts[0]->hBstr, sts[0]->hBstr->nb_ind_tot ); reset_indices_enc( sts[1]->hBstr, sts[1]->hBstr->nb_ind_tot ); reset_indices_enc( sts[1]->hBstr, sts[1]->hBstr->nb_ind_tot ); /* synchronize SID sending for variable SID rate */ if ( sts[0]->core_brate != sts[1]->core_brate ) Loading