Commit f7008ecf authored by fotopoulou's avatar fotopoulou
Browse files

fix crash with IGF and bandwidth switching when DTX is enabled

parent ce3afad1

lib_com/options.h

+1 −0
Original line number Diff line number Diff line
@@ -168,6 +168,7 @@ 
/*#define FIX_I4_OL_PITCH*/                             /* fix open-loop pitch used for EVS core switching */

#define FIX_1119_SPLIT_RENDERING_VOIP                   /* FhG: Add split rendering support to decoder in VoIP mode */

#define TMP_1342_WORKAROUND_DEC_FLUSH_BROKEN_IN_SR      /* FhG: Temporary workaround for incorrect implementation of decoder flush with split rendering */

#define FIX_1411_IGF_CRASH_BW_SWITCHING                 /* FhG: Fix for issue 1411: fixes crash that can happen for IGF with BW switching and DTX*/





/* #################### End BE switches ################################## */

lib_enc/ivas_cpe_enc.c

+35 −23
Original line number Diff line number Diff line
@@ -528,6 +528,10 @@ ivas_error ivas_cpe_enc( 
     * Core codec configuration

     *----------------------------------------------------------------*/



#ifdef FIX_1411_IGF_CRASH_BW_SWITCHING

    if ( !( sts[0]->core_brate == SID_2k40 || sts[0]->core_brate == FRAME_NO_DATA ) ) /* Reconfigurations not needed with DTX*/

    {

#endif

        if ( hCPE->element_mode == IVAS_CPE_MDCT && st_ivas->hMCT == NULL )

        {

            /* set coded BW for MDCT stereo */
@@ -552,7 +556,12 @@ ivas_error ivas_cpe_enc( 
        /* IGF reconfiguration */

        for ( n = 0; n < n_CoreChannels; n++ )

        {

        if ( ( hCPE->last_element_brate != hCPE->element_brate || hCPE->element_mode != hCPE->last_element_mode || ( hCPE->element_mode == IVAS_CPE_TD && sts[0]->bits_frame_nominal != last_bits_frame_nominal ) || sts[n]->last_bwidth != sts[n]->bwidth ) && ( n == 0 || hCPE->element_mode == IVAS_CPE_MDCT ) )

            if ( ( hCPE->last_element_brate != hCPE->element_brate || hCPE->element_mode != hCPE->last_element_mode || ( hCPE->element_mode == IVAS_CPE_TD && sts[0]->bits_frame_nominal != last_bits_frame_nominal ) || sts[n]->last_bwidth != sts[n]->bwidth

#ifdef FIX_1411_IGF_CRASH_BW_SWITCHING

                   || ( sts[n]->last_core_brate == SID_2k40 || sts[n]->last_core_brate == FRAME_NO_DATA )

#endif

                       ) &&

                 ( n == 0 || hCPE->element_mode == IVAS_CPE_MDCT ) )

            {

                int16_t igf;

                int16_t bw;
@@ -565,6 +574,9 @@ ivas_error ivas_cpe_enc( 
                }

            }

        }

#ifdef FIX_1411_IGF_CRASH_BW_SWITCHING

    }

#endif



    /* set ACELP@12k8 / ACELP@16k flag for flexible ACELP core */

    for ( n = 0; n < n_CoreChannels; n++ )