Loading lib_dec/dec_tcx_fx.c +11 −0 Original line number Diff line number Diff line Loading @@ -3450,7 +3450,18 @@ void IMDCT_ivas_fx( acelp_mem_len = 0; move16(); } #ifdef FIX_1348_BIT_PRECISION_IMPROVEMENT_QWIN IF( EQ_16( st->element_mode, IVAS_CPE_MDCT ) && ( LE_32( st->last_core_brate, SID_2k40 ) || st->last_core == ACELP_CORE ) && ( fullbandScale == 0 ) ) { /* Increase headroom because if the ACELP ZIR is used below, the synthesis filter gain is unknown. */ IF ( allow_qwin_change ) { allow_qwin_change = 0; move16(); q_win = s_max( -2, sub( q_win, 2 ) ); } } IF( EQ_16( kernel_type, MDST_IV ) ) { TCX_MDST_Inverse_qwin_fx( x_fx, x_e_hdrm, xn_buf_fx, overlap, L_frame - overlap, overlap, &q_win, allow_qwin_change ); Loading Loading
lib_dec/dec_tcx_fx.c +11 −0 Original line number Diff line number Diff line Loading @@ -3450,7 +3450,18 @@ void IMDCT_ivas_fx( acelp_mem_len = 0; move16(); } #ifdef FIX_1348_BIT_PRECISION_IMPROVEMENT_QWIN IF( EQ_16( st->element_mode, IVAS_CPE_MDCT ) && ( LE_32( st->last_core_brate, SID_2k40 ) || st->last_core == ACELP_CORE ) && ( fullbandScale == 0 ) ) { /* Increase headroom because if the ACELP ZIR is used below, the synthesis filter gain is unknown. */ IF ( allow_qwin_change ) { allow_qwin_change = 0; move16(); q_win = s_max( -2, sub( q_win, 2 ) ); } } IF( EQ_16( kernel_type, MDST_IV ) ) { TCX_MDST_Inverse_qwin_fx( x_fx, x_e_hdrm, xn_buf_fx, overlap, L_frame - overlap, overlap, &q_win, allow_qwin_change ); Loading