Loading lib_dec/ivas_mdct_core_dec_fx.c +4 −0 Original line number Diff line number Diff line Loading @@ -1384,6 +1384,10 @@ void ivas_mdct_core_reconstruct_fx( } ELSE /*ACELP core for ACELP-PLC */ { #ifdef FIX_1348_BIT_PRECISION_IMPROVEMENT_QWIN Copy( st->hTcxDec->old_synth, synth_buf_fx, st->hTcxDec->old_synth_len ); // Q = st->hTcxDec->q_old_synth Copy_Scale_sig( st->hTcxDec->old_synthFB_fx, synth_bufFB_fx, st->hTcxDec->old_synth_lenFB, sub( st->hTcxDec->q_old_synth, st->Q_syn ) ); // Q = st->hTcxDec->q_old_synth #endif assert( EQ_16( st->bfi, 1 ) ); /* PLC: [TCX: TD PLC] */ IF( MCT_flag != 0 ) Loading Loading
lib_dec/ivas_mdct_core_dec_fx.c +4 −0 Original line number Diff line number Diff line Loading @@ -1384,6 +1384,10 @@ void ivas_mdct_core_reconstruct_fx( } ELSE /*ACELP core for ACELP-PLC */ { #ifdef FIX_1348_BIT_PRECISION_IMPROVEMENT_QWIN Copy( st->hTcxDec->old_synth, synth_buf_fx, st->hTcxDec->old_synth_len ); // Q = st->hTcxDec->q_old_synth Copy_Scale_sig( st->hTcxDec->old_synthFB_fx, synth_bufFB_fx, st->hTcxDec->old_synth_lenFB, sub( st->hTcxDec->q_old_synth, st->Q_syn ) ); // Q = st->hTcxDec->q_old_synth #endif assert( EQ_16( st->bfi, 1 ) ); /* PLC: [TCX: TD PLC] */ IF( MCT_flag != 0 ) Loading