Merge branch 'main' into 1366-improve-wmops-of-sns_1st_cod_fx (149df281) · Commits · SA4 / Audio / IVAS BASOP

Workspace_msvc/lib_com.vcxproj

+0 −2

Original line number	Diff line number	Diff line
		@@ -277,7 +277,6 @@
		<ClCompile Include="..\lib_com\swb_bwe_com_fx.c" />
		<ClCompile Include="..\lib_com\swb_bwe_com_hr_fx.c" />
		<ClCompile Include="..\lib_com\swb_bwe_com_lr_fx.c" />
		<ClCompile Include="..\lib_com\swb_tbe_com.c" />
		<ClCompile Include="..\lib_com\swb_tbe_com_fx.c" />
		<ClCompile Include="..\lib_com\syn_12k8_fx.c" />
		<ClCompile Include="..\lib_com\syn_filt_fx.c" />
		@@ -316,7 +315,6 @@
		<ClInclude Include="..\lib_com\ivas_cnst.h" />
		<ClInclude Include="..\lib_com\ivas_error.h" />
		<ClInclude Include="..\lib_com\ivas_error_utils.h" />
		<ClInclude Include="..\lib_com\ivas_prot.h" />
		<ClInclude Include="..\lib_com\ivas_prot_fx.h" />
		<ClInclude Include="..\lib_com\ivas_rom_com.h" />
		<ClInclude Include="..\lib_com\ivas_stat_com.h" />

Workspace_msvc/lib_com.vcxproj.filters

+0 −6

Original line number	Diff line number	Diff line
		@@ -430,9 +430,6 @@
		<ClCompile Include="..\lib_com\rom_com.c">
		<Filter>common_all_c</Filter>
		</ClCompile>
		<ClCompile Include="..\lib_com\swb_tbe_com.c">
		<Filter>common_all_c</Filter>
		</ClCompile>
		<ClCompile Include="..\lib_com\tcx_mdct_window.c">
		<Filter>common_all_c</Filter>
		</ClCompile>
		@@ -573,9 +570,6 @@
		<ClInclude Include="..\lib_com\ivas_error_utils.h">
		<Filter>common_h</Filter>
		</ClInclude>
		<ClInclude Include="..\lib_com\ivas_prot.h">
		<Filter>common_h</Filter>
		</ClInclude>
		<ClInclude Include="..\lib_com\ivas_rom_com.h">
		<Filter>common_h</Filter>
		</ClInclude>

lib_com/bitstream.c

+0 −275

Original line number	Diff line number	Diff line
		@@ -1660,281 +1660,6 @@ static void decoder_selectCodec(
		return;
		}

		/-------------------------------------------------------------------
		* dec_prm_core()
		*
		*
		-------------------------------------------------------------------/

		static void dec_prm_core(
		Decoder_State *st )
		{
		int16_t n, frame_size_index = -1;

		st->core = -1;

		if ( st->total_brate == FRAME_NO_DATA )
		{
		st->m_frame_type = ZERO_FRAME;
		}
		else if ( st->total_brate == SID_2k40 )
		{
		st->m_frame_type = SID_FRAME;
		}
		else
		{
		st->m_frame_type = ACTIVE_FRAME;
		for ( n = 0; n < FRAME_SIZE_NB; ++n )
		{
		if ( FrameSizeConfig[n].frame_bits == st->total_brate / FRAMES_PER_SEC )
		{
		frame_size_index = n;
		break;
		}
		}

		/* Get audio bandwidth info */
		st->bwidth = get_next_indice( st, FrameSizeConfig[frame_size_index].bandwidth_bits );
		st->bwidth += FrameSizeConfig[frame_size_index].bandwidth_min;
		if ( st->bwidth > FB )
		{
		st->bwidth = FB;
		st->BER_detect = 1;
		}

		if ( st->bwidth > SWB && st->total_brate < ACELP_16k40 )
		{
		st->bwidth = SWB;
		st->BER_detect = 1;
		}
		/* Skip reserved bit */
		get_next_indice_tmp( st, FrameSizeConfig[frame_size_index].reserved_bits );

		if ( get_next_indice_1( st ) ) /* TCX */
		{
		if ( get_next_indice_1( st ) )
		{
		st->core = HQ_CORE;
		}
		else
		{
		st->core = TCX_20_CORE;
		}
		}
		else /* ACELP */
		{
		st->core = ACELP_CORE;
		}
		}

		return;
		}

		/-----------------------------------------------------------------
		* decision_matrix_core_dec()
		*
		* Read core signaling bits from the bitstream
		* Set st->core, and st->bwidth if signalled together with the core.
		-----------------------------------------------------------------/

		static void decision_matrix_core_dec(
		Decoder_State st / i/o: decoder state structure */
		)
		{
		int16_t start_idx;
		int32_t ind;
		int16_t nBits;

		assert( st->bfi != 1 );

		st->core = -1;
		st->bwidth = -1;

		if ( st->total_brate == FRAME_NO_DATA \|\| st->total_brate == SID_2k40 )
		{
		st->core = ACELP_CORE;
		}
		/* SC-VBR */
		else if ( st->total_brate == PPP_NELP_2k80 )
		{
		st->core = ACELP_CORE;
		return;
		}

		/---------------------------------------------------------------------
		* ACELP/HQ core selection
		---------------------------------------------------------------------/

		if ( st->total_brate < ACELP_24k40 )
		{
		st->core = ACELP_CORE;
		}
		else if ( st->total_brate >= ACELP_24k40 && st->total_brate <= ACELP_64k )
		{
		/* read the ACELP/HQ core selection bit */
		st->core = get_next_indice( st, 1 ) * HQ_CORE;
		}
		else
		{
		st->core = HQ_CORE;
		}

		/-----------------------------------------------------------------
		* Read ACELP signaling bits from the bitstream
		-----------------------------------------------------------------/

		if ( st->core == ACELP_CORE )
		{
		/* find the section in the ACELP signaling table corresponding to bitrate */
		start_idx = 0;
		while ( acelp_sig_tbl[start_idx] != st->total_brate )
		{
		start_idx++;
		}

		/* skip the bitrate */
		start_idx += 1;

		/* retrieve the number of bits */
		nBits = (int16_t) acelp_sig_tbl[start_idx++];

		/* retrieve the signaling indice */
		ind = acelp_sig_tbl[start_idx + get_next_indice( st, nBits )];
		st->bwidth = ( ind >> 3 ) & 0x7;

		/* convert signaling indice into signaling information */
		if ( ( ind & 0x7 ) == LR_MDCT )
		{
		st->core = HQ_CORE;
		}
		}

		/-----------------------------------------------------------------
		* Read HQ signaling bits from the bitstream
		* Set HQ core type
		-----------------------------------------------------------------/

		if ( st->core == HQ_CORE )
		{
		/* read the HQ/TCX core switching flag */
		if ( get_next_indice( st, 1 ) )
		{
		st->core = TCX_20_CORE;
		}

		/* For TCX: read/set band-width (needed for different I/O sampling rate support) */
		if ( st->core == TCX_20_CORE && st->total_brate > ACELP_16k40 )
		{
		ind = get_next_indice( st, 2 );

		if ( ind == 0 )
		{
		st->bwidth = NB;
		}
		else if ( ind == 1 )
		{
		st->bwidth = WB;
		}
		else if ( ind == 2 )
		{
		st->bwidth = SWB;
		}
		else
		{
		st->bwidth = FB;
		}
		}
		}

		return;
		}

		/-------------------------------------------------------------------
		* mdct_switching_dec()
		*
		* Set up MDCT core switching if indicated in the bitstream
		-------------------------------------------------------------------/

		void mdct_switching_dec_ivas_fx(
		Decoder_State st / i/o: decoder state structure */
		)
		{
		if ( !st->bfi )
		{

		if ( st->Opt_AMR_WB )
		{
		return;
		}


		if ( st->total_brate == ACELP_13k20 \|\| st->total_brate == ACELP_32k )
		{
		st->mdct_sw_enable = MODE1;
		}
		else if ( ACELP_16k40 <= st->total_brate && st->total_brate <= ACELP_24k40 )
		{
		st->mdct_sw_enable = MODE2;
		}

		if ( st->codec_mode == MODE1 && st->mdct_sw_enable == MODE1 )
		{
		/* Read ahead core signaling */
		int16_t next_bit_pos_save = st->next_bit_pos;
		int16_t core_save = st->core;
		int16_t bwidth_save = st->bwidth;

		decision_matrix_core_dec( st ); /* sets st->core */

		if ( st->core == TCX_20_CORE )
		{
		/* Trigger TCX */
		st->codec_mode = MODE2;
		st->mdct_sw = MODE1;
		}
		else
		{
		/* Rewind bitstream */
		st->next_bit_pos = next_bit_pos_save;
		if ( st->bfi )
		{
		st->core = core_save;
		st->bwidth = bwidth_save;
		}
		}
		}
		else if ( st->codec_mode == MODE2 && st->mdct_sw_enable == MODE2 )
		{
		/* Read ahead core signaling */
		int16_t next_bit_pos_save = st->next_bit_pos;
		int16_t core_save = st->core;
		int16_t bwidth_save = st->bwidth;

		dec_prm_core( st ); /* sets st->core */

		if ( st->core == HQ_CORE )
		{
		/* Trigger HQ_CORE */
		st->codec_mode = MODE1;
		st->mdct_sw = MODE2;
		}
		else
		{
		/* Rewind bitstream */
		st->next_bit_pos = next_bit_pos_save;
		if ( st->bfi )
		{
		st->core = core_save;
		}
		/* always reset bwidth, to not interfere with BER logic */
		st->bwidth = bwidth_save;
		}
		}
		}

		return;
		}


		/-------------------------------------------------------------------
		* reset_elements()

lib_com/bitstream_fx.c

+142 −959

File changed.

Preview size limit exceeded, changes collapsed.

lib_com/cldfb.c

+54 −20

Original line number	Diff line number	Diff line
		@@ -1101,6 +1101,9 @@ void cldfbSynthesis_ivas_fx(
		Word32 *imagBuffer_fx, / i : imag values Qx*/
		Word32 timeOut_fx, / o : output time domain samples Qx - 1*/
		const Word16 samplesToProcess, /* i : number of processed samples */
		#ifdef OPT_SBA_AVOID_SPAR_RESCALE
		const Word16 shift, /* i : scale for state buffer */
		#endif /* OPT_SBA_AVOID_SPAR_RESCALE */
		HANDLE_CLDFB_FILTER_BANK h_cldfb /* i : filter bank state */
		)
		{
		@@ -1266,6 +1269,10 @@ void cldfbSynthesis_ivas_fx(
		}

		/* synthesis prototype filter */
		#ifdef OPT_SBA_AVOID_SPAR_RESCALE
		IF( 0 == shift )
		{
		#endif /* OPT_SBA_AVOID_SPAR_RESCALE */
		FOR( i = 0; i < L2; i++ )
		{
		accu0 = Madd_32_16( synthesisBuffer_fx[i], Mpy_32_16_1( new_samples_fx[L2 - 1 - i], p_filter[i] ), p_filter_sf ); // Qx - 1
		@@ -1285,6 +1292,33 @@ void cldfbSynthesis_ivas_fx(
		synthesisBuffer_fx[4 * L2 + i] = accu4;
		move32();
		}
		#ifdef OPT_SBA_AVOID_SPAR_RESCALE
		}
		ELSE
		{

		FOR( i = 0; i < L2; i++ )
		{
		Word32 prod = L_shl_sat( Mpy_32_16_1( new_samples_fx[L2 - 1 - i], p_filter_sf ), shift );
		accu0 = Madd_32_16( synthesisBuffer_fx[i], prod, p_filter[i] ); // Qx - 1
		accu1 = Madd_32_16( synthesisBuffer_fx[1 * L2 + i], prod, p_filter[( 1 * L2 + i )] ); // Qx - 1
		accu2 = Madd_32_16( synthesisBuffer_fx[2 * L2 + i], prod, p_filter[( 2 * L2 + i )] ); // Qx - 1
		accu3 = Madd_32_16( synthesisBuffer_fx[3 * L2 + i], prod, p_filter[( 3 * L2 + i )] ); // Qx - 1
		accu4 = Madd_32_16( synthesisBuffer_fx[4 * L2 + i], prod, p_filter[( 4 * L2 + i )] ); // Qx - 1

		synthesisBuffer_fx[i] = accu0;
		move32();
		synthesisBuffer_fx[1 * L2 + i] = accu1;
		move32();
		synthesisBuffer_fx[2 * L2 + i] = accu2;
		move32();
		synthesisBuffer_fx[3 * L2 + i] = accu3;
		move32();
		synthesisBuffer_fx[4 * L2 + i] = accu4;
		move32();
		}
		}
		#endif /* OPT_SBA_AVOID_SPAR_RESCALE */

		FOR( i = 0; i < M1; i++ )
		{