Commit d9be453d authored by malenov's avatar malenov
Browse files

dumping core.loc2, coder_type and ism_imp

parent a7f9fcc5

lib_enc/ivas_core_pre_proc_front.c

+14 −0
Original line number Diff line number Diff line
@@ -1456,6 +1456,20 @@ ivas_error pre_proc_front_ivas_fx( 


    Copy_Scale_sig_16_32( st->lgBin_E_fx, st->Bin_E_fx, L_FFT / 2, sub( st->q_Bin_E, Q7 ) );



#ifdef DEBUG_FORCE_DIR

    if ( st->force_dir[0] != '\0' )

    {

        dbgread( &st->coder_type, sizeof( int16_t ), 1, fname( st->force_dir, "force_coder_type.enf", -1, -1, -1 ) );

        dbgread( &st->coder_type_raw, sizeof( int16_t ), 1, fname( st->force_dir, "force_coder_type_raw.enf", -1, -1, -1 ) );

    }

    else

    {

        dbgwrite( &st->coder_type, sizeof( int16_t ), 1, 1, "res/force_coder_type.enf" );

        dbgwrite( &st->coder_type_raw, sizeof( int16_t ), 1, 1, "res/force_coder_type_raw.enf" );

    }

#endif





    /*-----------------------------------------------------------------*

     * channel aware mode configuration                                *

     *-----------------------------------------------------------------*/

lib_enc/ivas_decision_matrix_enc.c

+22 −11
Original line number Diff line number Diff line
@@ -207,6 +207,17 @@ void ivas_decision_matrix_enc_fx( 
    test();

    test();



#ifdef DEBUG_FORCE_DIR

    if ( st->force_dir[0] != '\0' )

    {

        dbgread( &st->core, sizeof( int16_t ), 1, fname( st->force_dir, "force_core_loc1.enf", -1, -1, -1 ) );

    }

    else

    {

        dbgwrite( &st->core, sizeof( int16_t ), 1, 1, "res/force_core_loc1.enf" );

    }

#endif



    /* do not allow TD stereo ACELP core -> DFT stereo TCX core switching as it is on the WC complexity path */

    if ( ( ( st->last_core == ACELP_CORE && EQ_16( last_element_mode, IVAS_CPE_TD ) && EQ_16( st->element_mode, IVAS_CPE_DFT ) ) || ( EQ_16( st->tdm_LRTD_flag, 1 ) && LE_32( st->total_brate, IVAS_16k4 ) ) ) && EQ_16( st->core, TCX_20_CORE ) && LE_32( st->total_brate, MAX_ACELP_BRATE ) ) /* Override TCX in case of LRTD && primary channel has low bitrate*/

    {
@@ -255,17 +266,6 @@ void ivas_decision_matrix_enc_fx( 
    }

#endif



#ifdef DEBUG_FORCE_DIR

    if ( st->force_dir[0] != '\0' )

    {

        dbgread( &st->core, sizeof( int16_t ), 1, fname( st->force_dir, "force_core.enf", -1, -1, -1 ) );

    }

    else

    {

        dbgwrite( &st->core, sizeof( int16_t ), 1, 1, "res/force_core.enf" );

    }

#endif



    /* TCX not available at low bitrates -> replace it by GSC */

    test();

    IF( EQ_16( st->core, TCX_20_CORE ) && LT_32( st->total_brate, STEREO_TCX_MIN_RATE ) )
@@ -305,6 +305,17 @@ void ivas_decision_matrix_enc_fx( 
        move16();

    }



#ifdef DEBUG_FORCE_DIR

    if ( st->force_dir[0] != '\0' )

    {

        dbgread( &st->core, sizeof( int16_t ), 1, fname( st->force_dir, "force_core_loc2.enf", -1, -1, -1 ) );

    }

    else

    {

        dbgwrite( &st->core, sizeof( int16_t ), 1, 1, "res/force_core_loc2.enf" );

    }

#endif



    /*---------------------------------------------------------------------*

     * Select ACELP and GSC extension layer

     *---------------------------------------------------------------------*/

lib_enc/ivas_ism_enc.c

+19 −0
Original line number Diff line number Diff line
@@ -228,6 +228,11 @@ ivas_error ivas_ism_enc_fx( 


        st->bits_frame_nominal = sub( extract_l( Mpy_32_32( hSCE->element_brate, ONE_BY_FRAMES_PER_SEC_Q31 ) ), ISM_NB_BITS_METADATA_NOMINAL );

        move16();



#ifdef DEBUG_MODE_INFO

        dbgwrite( &st->element_mode, sizeof( int16_t ), 1, input_frame, fname( debug_dir, "element_mode", 0, st->id_element, ENC ) );

#endif



        /*----------------------------------------------------------------*

         * Front Pre-processing

         *----------------------------------------------------------------*/
@@ -506,6 +511,20 @@ ivas_error ivas_ism_enc_fx( 
        }

    }



#ifdef DEBUG_MODE_INFO

    for ( sce_id = 0; sce_id < nchan_transport_ism; sce_id++ )

    {

        float tmpF;

        int16_t id;



        st = st_ivas->hSCE[sce_id]->hCoreCoder[0];

        id = st->id_element;



        tmpF = st->element_brate / 1000.0f;

        dbgwrite( &tmpF, sizeof( float ), 1, input_frame, fname( debug_dir, "element_brate", 0, id, ENC ) );

    }

#endif



    pop_wmops();



    return error;

lib_enc/ivas_ism_metadata_enc.c

+11 −0
Original line number Diff line number Diff line
@@ -338,6 +338,17 @@ ivas_error ivas_ism_metadata_enc_fx( 
        }

    }



#ifdef DEBUG_FORCE_DIR

    if ( hSCE[0]->hCoreCoder[0]->force_dir[0] != '\0' )

    {

        dbgread( ism_imp, sizeof( int16_t ), nchan_ism, fname( hSCE[0]->hCoreCoder[0]->force_dir, "force_ism_imp.enf", -1, -1, -1 ) );

    }

    else

    {

        dbgwrite( ism_imp, sizeof( int16_t ), nchan_ism, 1, "res/force_ism_imp.enf" );

    }

#endif



    /*----------------------------------------------------------------*

     * Write ISM common signaling

     *----------------------------------------------------------------*/