Loading lib_dec/core_switching_dec.c +1 −1 Original line number Diff line number Diff line Loading @@ -264,7 +264,7 @@ ivas_error core_switching_pre_dec( } #ifdef NONBE_1214_PLC_LSF_MEMORY if ( ( ( st->core == ACELP_CORE || st->core == AMR_WB_CORE ) && ( st->last_core == HQ_CORE || last_element_mode == IVAS_CPE_MDCT ) ) || if ( ( ( st->core == ACELP_CORE || st->core == AMR_WB_CORE ) && ( st->last_core == HQ_CORE || ( last_element_mode == IVAS_CPE_MDCT && st->core_brate != FRAME_NO_DATA && st->core_brate != SID_2k40 ) ) ) || ( ( st->element_mode == IVAS_CPE_DFT || st->element_mode == IVAS_CPE_TD || ( st->element_mode == IVAS_CPE_MDCT && last_element_mode == IVAS_CPE_DFT ) ) && nchan_out == 2 && st->core_brate != SID_2k40 && st->core_brate != FRAME_NO_DATA && ( last_core_brate_st0 == FRAME_NO_DATA || last_core_brate_st0 == SID_2k40 ) ) ) #else Loading Loading
lib_dec/core_switching_dec.c +1 −1 Original line number Diff line number Diff line Loading @@ -264,7 +264,7 @@ ivas_error core_switching_pre_dec( } #ifdef NONBE_1214_PLC_LSF_MEMORY if ( ( ( st->core == ACELP_CORE || st->core == AMR_WB_CORE ) && ( st->last_core == HQ_CORE || last_element_mode == IVAS_CPE_MDCT ) ) || if ( ( ( st->core == ACELP_CORE || st->core == AMR_WB_CORE ) && ( st->last_core == HQ_CORE || ( last_element_mode == IVAS_CPE_MDCT && st->core_brate != FRAME_NO_DATA && st->core_brate != SID_2k40 ) ) ) || ( ( st->element_mode == IVAS_CPE_DFT || st->element_mode == IVAS_CPE_TD || ( st->element_mode == IVAS_CPE_MDCT && last_element_mode == IVAS_CPE_DFT ) ) && nchan_out == 2 && st->core_brate != SID_2k40 && st->core_brate != FRAME_NO_DATA && ( last_core_brate_st0 == FRAME_NO_DATA || last_core_brate_st0 == SID_2k40 ) ) ) #else Loading